From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50999) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W5hgk-00058Y-Jn for qemu-devel@nongnu.org; Tue, 21 Jan 2014 15:12:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W5hgj-0007bo-I5 for qemu-devel@nongnu.org; Tue, 21 Jan 2014 15:12:46 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:44951) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W5hgj-0007WW-AZ for qemu-devel@nongnu.org; Tue, 21 Jan 2014 15:12:45 -0500 From: Peter Maydell Date: Tue, 21 Jan 2014 20:12:14 +0000 Message-Id: <1390335150-13470-9-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1390335150-13470-1-git-send-email-peter.maydell@linaro.org> References: <1390335150-13470-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 08/24] target-arm: A64: Implement MSR (immediate) instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Crosthwaite , patches@linaro.org, Michael Matz , Alexander Graf , Claudio Fontana , Dirk Mueller , Will Newton , Laurent Desnogues , =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvmarm@lists.cs.columbia.edu, Christoffer Dall , Richard Henderson Implement the MSR (immediate) instructions, which can update the PSTATE SP and DAIF fields. --- target-arm/cpu.h | 1 + target-arm/helper.h | 2 ++ target-arm/op_helper.c | 25 +++++++++++++++++++++++++ target-arm/translate-a64.c | 24 +++++++++++++++++++++++- 4 files changed, 51 insertions(+), 1 deletion(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 1966a19..1dce28b 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -431,6 +431,7 @@ int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw, #define PSTATE_Z (1U << 30) #define PSTATE_N (1U << 31) #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) +#define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) #define CACHED_PSTATE_BITS (PSTATE_NZCV) /* Mode values for AArch64 */ #define PSTATE_MODE_EL3h 13 diff --git a/target-arm/helper.h b/target-arm/helper.h index 70872df..638c91a 100644 --- a/target-arm/helper.h +++ b/target-arm/helper.h @@ -62,6 +62,8 @@ DEF_HELPER_2(get_cp_reg, i32, env, ptr) DEF_HELPER_3(set_cp_reg64, void, env, ptr, i64) DEF_HELPER_2(get_cp_reg64, i64, env, ptr) +DEF_HELPER_3(msr_i_pstate, void, env, i32, i32) + DEF_HELPER_2(get_r13_banked, i32, env, i32) DEF_HELPER_3(set_r13_banked, void, env, i32, i32) diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index a918e5b..c812a9f 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -313,6 +313,31 @@ uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip) return value; } +void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t op, uint32_t imm) +{ + /* MSR_i to update PSTATE. This is OK from EL0 only if UMA is set. + * Note that SPSel is never OK from EL0; we rely on handle_msr_i() + * to catch that case at translate time. + */ + if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UMA)) { + raise_exception(env, EXCP_UDEF); + } + + switch (op) { + case 0x05: /* SPSel */ + env->pstate = deposit32(env->pstate, 0, 1, imm); + break; + case 0x1e: /* DAIFSet */ + env->pstate |= (imm << 6) & PSTATE_DAIF; + break; + case 0x1f: /* DAIFClear */ + env->pstate &= ~((imm << 6) & PSTATE_DAIF); + break; + default: + g_assert_not_reached(); + } +} + /* ??? Flag setting arithmetic is awkward because we need to do comparisons. The only way to do that in TCG is a conditional branch, which clobbers all our temporaries. For now implement these as helper functions. */ diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 5aa1f17..802d733 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -1055,7 +1055,29 @@ static void handle_sync(DisasContext *s, uint32_t insn, static void handle_msr_i(DisasContext *s, uint32_t insn, unsigned int op1, unsigned int op2, unsigned int crm) { - unsupported_encoding(s, insn); + int op = op1 << 3 | op2; + switch (op) { + case 0x05: /* SPSel */ + if (s->current_pl == 0) { + unallocated_encoding(s); + return; + } + /* fall through */ + case 0x1e: /* DAIFSet */ + case 0x1f: /* DAIFClear */ + { + TCGv_i32 tcg_imm = tcg_const_i32(crm); + TCGv_i32 tcg_op = tcg_const_i32(op); + gen_helper_msr_i_pstate(cpu_env, tcg_op, tcg_imm); + tcg_temp_free_i32(tcg_imm); + tcg_temp_free_i32(tcg_op); + s->is_jmp = DISAS_UPDATE; + break; + } + default: + unallocated_encoding(s); + return; + } } static void gen_get_nzcv(TCGv_i64 tcg_rt) -- 1.8.5