From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48410) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W7VM5-0004w6-4Z for qemu-devel@nongnu.org; Sun, 26 Jan 2014 14:26:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W7VM4-0000rh-0Y for qemu-devel@nongnu.org; Sun, 26 Jan 2014 14:26:53 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:45179) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W7VM3-0000qV-Pm for qemu-devel@nongnu.org; Sun, 26 Jan 2014 14:26:51 -0500 From: Peter Maydell Date: Sun, 26 Jan 2014 19:24:53 +0000 Message-Id: <1390764312-21789-3-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1390764312-21789-1-git-send-email-peter.maydell@linaro.org> References: <1390764312-21789-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 02/21] target-arm: A64: Add SIMD three-different ABDL instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Crosthwaite , patches@linaro.org, Michael Matz , Alexander Graf , Claudio Fontana , Dirk Mueller , Will Newton , Laurent Desnogues , =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvmarm@lists.cs.columbia.edu, Christoffer Dall , Richard Henderson Implement the absolute-difference instructions in the SIMD three-different group: SABAL, SABAL2, UABAL, UABAL2, SABDL, SABDL2, UABDL, UABDL2. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target-arm/translate-a64.c | 35 +++++++++++++++++++++++++++++++++-- 1 file changed, 33 insertions(+), 2 deletions(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 924a539..145125e 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -5630,6 +5630,21 @@ static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size, } switch (opcode) { + case 5: /* SABAL, SABAL2, UABAL, UABAL2 */ + case 7: /* SABDL, SABDL2, UABDL, UABDL2 */ + { + TCGv_i64 tcg_tmp1 = tcg_temp_new_i64(); + TCGv_i64 tcg_tmp2 = tcg_temp_new_i64(); + + tcg_gen_sub_i64(tcg_tmp1, tcg_op1, tcg_op2); + tcg_gen_sub_i64(tcg_tmp2, tcg_op2, tcg_op1); + tcg_gen_movcond_i64(is_u ? TCG_COND_GEU : TCG_COND_GE, + tcg_passres, + tcg_op1, tcg_op2, tcg_tmp1, tcg_tmp2); + tcg_temp_free_i64(tcg_tmp1); + tcg_temp_free_i64(tcg_tmp2); + break; + } case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ case 12: /* UMULL, UMULL2, SMULL, SMULL2 */ @@ -5668,6 +5683,22 @@ static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size, } switch (opcode) { + case 5: /* SABAL, SABAL2, UABAL, UABAL2 */ + case 7: /* SABDL, SABDL2, UABDL, UABDL2 */ + if (size == 0) { + if (is_u) { + gen_helper_neon_abdl_u16(tcg_passres, tcg_op1, tcg_op2); + } else { + gen_helper_neon_abdl_s16(tcg_passres, tcg_op1, tcg_op2); + } + } else { + if (is_u) { + gen_helper_neon_abdl_u32(tcg_passres, tcg_op1, tcg_op2); + } else { + gen_helper_neon_abdl_s32(tcg_passres, tcg_op1, tcg_op2); + } + } + break; case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ case 12: /* UMULL, UMULL2, SMULL, SMULL2 */ @@ -5767,10 +5798,10 @@ static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn) /* fall through */ case 0: case 2: - case 5: - case 7: unsupported_encoding(s, insn); break; + case 5: + case 7: case 8: case 10: case 12: -- 1.8.5