From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48503) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W7VM9-00053o-9j for qemu-devel@nongnu.org; Sun, 26 Jan 2014 14:26:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W7VM8-0000un-B2 for qemu-devel@nongnu.org; Sun, 26 Jan 2014 14:26:57 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:45179) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W7VM8-0000qV-1p for qemu-devel@nongnu.org; Sun, 26 Jan 2014 14:26:56 -0500 From: Peter Maydell Date: Sun, 26 Jan 2014 19:24:55 +0000 Message-Id: <1390764312-21789-5-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1390764312-21789-1-git-send-email-peter.maydell@linaro.org> References: <1390764312-21789-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 04/21] target-arm: A64: Add top level decode for SIMD 3-same group List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Crosthwaite , patches@linaro.org, Michael Matz , Alexander Graf , Claudio Fontana , Dirk Mueller , Will Newton , Laurent Desnogues , =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvmarm@lists.cs.columbia.edu, Christoffer Dall , Richard Henderson Add top level decode for the A64 SIMD three regs same group (C3.6.16), splitting it into the pairwise, logical, float and integer subgroups. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target-arm/translate-a64.c | 45 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 6ff3e43..2079c96 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -5948,6 +5948,30 @@ static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn) } } +/* Logic op (opcode == 3) subgroup of C3.6.16. */ +static void disas_simd_3same_logic(DisasContext *s, uint32_t insn) +{ + unsupported_encoding(s, insn); +} + +/* Pairwise op subgroup of C3.6.16. */ +static void disas_simd_3same_pair(DisasContext *s, uint32_t insn) +{ + unsupported_encoding(s, insn); +} + +/* Floating point op subgroup of C3.6.16. */ +static void disas_simd_3same_float(DisasContext *s, uint32_t insn) +{ + unsupported_encoding(s, insn); +} + +/* Integer op subgroup of C3.6.16. */ +static void disas_simd_3same_int(DisasContext *s, uint32_t insn) +{ + unsupported_encoding(s, insn); +} + /* C3.6.16 AdvSIMD three same * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0 * +---+---+---+-----------+------+---+------+--------+---+------+------+ @@ -5956,7 +5980,26 @@ static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn) */ static void disas_simd_three_reg_same(DisasContext *s, uint32_t insn) { - unsupported_encoding(s, insn); + int opcode = extract32(insn, 11, 5); + + switch (opcode) { + case 0x3: /* logic ops */ + disas_simd_3same_logic(s, insn); + break; + case 0x17: /* ADDP */ + case 0x14: /* SMAXP, UMAXP */ + case 0x15: /* SMINP, UMINP */ + /* Pairwise operations */ + disas_simd_3same_pair(s, insn); + break; + case 0x18 ... 0x31: + /* floating point ops, sz[1] and U are part of opcode */ + disas_simd_3same_float(s, insn); + break; + default: + disas_simd_3same_int(s, insn); + break; + } } /* C3.6.17 AdvSIMD two reg misc -- 1.8.5