From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45537) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W86ks-0003qi-C9 for qemu-devel@nongnu.org; Tue, 28 Jan 2014 06:23:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W86kl-0000c9-Am for qemu-devel@nongnu.org; Tue, 28 Jan 2014 06:22:58 -0500 Received: from mail-la0-f45.google.com ([209.85.215.45]:65076) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W86kl-0000bu-3c for qemu-devel@nongnu.org; Tue, 28 Jan 2014 06:22:51 -0500 Received: by mail-la0-f45.google.com with SMTP id b8so203035lan.4 for ; Tue, 28 Jan 2014 03:22:50 -0800 (PST) From: Will Newton Date: Tue, 28 Jan 2014 11:22:30 +0000 Message-Id: <1390908155-23475-6-git-send-email-will.newton@linaro.org> In-Reply-To: <1390908155-23475-1-git-send-email-will.newton@linaro.org> References: <1390908155-23475-1-git-send-email-will.newton@linaro.org> Subject: [Qemu-devel] [PATCH v2 06/11] target-arm: Add support for AArch32 SIMD VRINTX List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , patches@linaro.org Add support for the AArch32 Advanced SIMD VRINTX instruction. Signed-off-by: Will Newton Reviewed-by: Peter Maydell --- target-arm/translate.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index 9eb5b92..c179817 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -4709,6 +4709,7 @@ static const uint8_t neon_3r_sizes[] = { #define NEON_2RM_VMOVN 36 /* Includes VQMOVN, VQMOVUN */ #define NEON_2RM_VQMOVN 37 /* Includes VQMOVUN */ #define NEON_2RM_VSHLL 38 +#define NEON_2RM_VRINTX 41 #define NEON_2RM_VCVT_F16_F32 44 #define NEON_2RM_VCVT_F32_F16 46 #define NEON_2RM_VRECPE 56 @@ -4724,7 +4725,7 @@ static int neon_2rm_is_float_op(int op) { /* Return true if this neon 2reg-misc op is float-to-float */ return (op == NEON_2RM_VABS_F || op == NEON_2RM_VNEG_F || - op >= NEON_2RM_VRECPE_F); + op == NEON_2RM_VRINTX || op >= NEON_2RM_VRECPE_F); } /* Each entry in this array has bit n set if the insn allows @@ -4768,6 +4769,7 @@ static const uint8_t neon_2rm_sizes[] = { [NEON_2RM_VMOVN] = 0x7, [NEON_2RM_VQMOVN] = 0x7, [NEON_2RM_VSHLL] = 0x7, + [NEON_2RM_VRINTX] = 0x4, [NEON_2RM_VCVT_F16_F32] = 0x2, [NEON_2RM_VCVT_F32_F16] = 0x2, [NEON_2RM_VRECPE] = 0x4, @@ -6480,6 +6482,13 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins } neon_store_reg(rm, pass, tmp2); break; + case NEON_2RM_VRINTX: + { + TCGv_ptr fpstatus = get_fpstatus_ptr(1); + gen_helper_rints_exact(cpu_F0s, cpu_F0s, fpstatus); + tcg_temp_free_ptr(fpstatus); + break; + } case NEON_2RM_VRECPE: gen_helper_recpe_u32(tmp, tmp, cpu_env); break; -- 1.8.1.4