From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59369) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W8FLA-0004Bv-Kk for qemu-devel@nongnu.org; Tue, 28 Jan 2014 15:33:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W8FL3-0005yF-0u for qemu-devel@nongnu.org; Tue, 28 Jan 2014 15:33:00 -0500 Received: from mail-pa0-f49.google.com ([209.85.220.49]:56835) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W8FL2-0005y3-RK for qemu-devel@nongnu.org; Tue, 28 Jan 2014 15:32:52 -0500 Received: by mail-pa0-f49.google.com with SMTP id hz1so838889pad.36 for ; Tue, 28 Jan 2014 12:32:51 -0800 (PST) From: Christoffer Dall Date: Tue, 28 Jan 2014 12:32:38 -0800 Message-Id: <1390941165-2079-2-git-send-email-christoffer.dall@linaro.org> In-Reply-To: <1390941165-2079-1-git-send-email-christoffer.dall@linaro.org> References: <1390941165-2079-1-git-send-email-christoffer.dall@linaro.org> Subject: [Qemu-devel] [PATCH v5 1/8] arm_gic: Introduce define for GIC_NR_SGIS List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: kvmarm@lists.cs.columbia.edu, Christoffer Dall , patches@linaro.org Instead of hardcoding 16 various places in the code, use a define to make it more clear what is going on. Signed-off-by: Christoffer Dall --- Changes [v1 -> v5]: - New patch in series hw/intc/arm_gic.c | 17 +++++++++++------ include/hw/intc/arm_gic_common.h | 1 + 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 9409684..98c6ff5 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -380,8 +380,10 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, irq = (offset - 0x100) * 8 + GIC_BASE_IRQ; if (irq >= s->num_irq) goto bad_reg; - if (irq < 16) - value = 0xff; + if (irq < GIC_NR_SGIS) { + value = 0xff; + } + for (i = 0; i < 8; i++) { if (value & (1 << i)) { int mask = @@ -406,8 +408,10 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, irq = (offset - 0x180) * 8 + GIC_BASE_IRQ; if (irq >= s->num_irq) goto bad_reg; - if (irq < 16) - value = 0; + if (irq < GIC_NR_SGIS) { + value = 0; + } + for (i = 0; i < 8; i++) { if (value & (1 << i)) { int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; @@ -423,8 +427,9 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, irq = (offset - 0x200) * 8 + GIC_BASE_IRQ; if (irq >= s->num_irq) goto bad_reg; - if (irq < 16) - irq = 0; + if (irq < GIC_NR_SGIS) { + irq = 0; + } for (i = 0; i < 8; i++) { if (value & (1 << i)) { diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h index 40cd3d6..dbf8787 100644 --- a/include/hw/intc/arm_gic_common.h +++ b/include/hw/intc/arm_gic_common.h @@ -27,6 +27,7 @@ #define GIC_MAXIRQ 1020 /* First 32 are private to each CPU (SGIs and PPIs). */ #define GIC_INTERNAL 32 +#define GIC_NR_SGIS 16 /* Maximum number of possible CPU interfaces, determined by GIC architecture */ #define GIC_NCPU 8 -- 1.8.5.2