From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48713) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W8VNQ-00019m-Dr for qemu-devel@nongnu.org; Wed, 29 Jan 2014 08:40:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W8VNG-0000rG-0g for qemu-devel@nongnu.org; Wed, 29 Jan 2014 08:40:24 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:45234) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W8VNF-0000p0-O2 for qemu-devel@nongnu.org; Wed, 29 Jan 2014 08:40:13 -0500 From: Peter Maydell Date: Wed, 29 Jan 2014 13:39:37 +0000 Message-Id: <1391002805-26596-11-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1391002805-26596-1-git-send-email-peter.maydell@linaro.org> References: <1391002805-26596-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 10/38] target-arm: A64: Add SIMD scalar copy instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anthony Liguori Cc: Blue Swirl , qemu-devel@nongnu.org, Aurelien Jarno Add support for the SIMD scalar copy instruction group (C3.6.7), which consists of the single instruction DUP (element, scalar). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target-arm/translate-a64.c | 43 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 69c75c0..7cfb55b 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -5108,6 +5108,35 @@ static void handle_simd_dupe(DisasContext *s, int is_q, int rd, int rn, tcg_temp_free_i64(tmp); } +/* C6.3.31 DUP (element, scalar) + * 31 21 20 16 15 10 9 5 4 0 + * +-----------------------+--------+-------------+------+------+ + * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd | + * +-----------------------+--------+-------------+------+------+ + */ +static void handle_simd_dupes(DisasContext *s, int rd, int rn, + int imm5) +{ + int size = ctz32(imm5); + int index; + TCGv_i64 tmp; + + if (size > 3) { + unallocated_encoding(s); + return; + } + + index = imm5 >> (size + 1); + + /* This instruction just extracts the specified element and + * zero-extends it into the bottom of the destination register. + */ + tmp = tcg_temp_new_i64(); + read_vec_element(s, tmp, rn, index, size); + write_fp_dreg(s, rd, tmp); + tcg_temp_free_i64(tmp); +} + /* C6.3.32 DUP (General) * * 31 30 29 21 20 16 15 10 9 5 4 0 @@ -5425,7 +5454,19 @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn) */ static void disas_simd_scalar_copy(DisasContext *s, uint32_t insn) { - unsupported_encoding(s, insn); + int rd = extract32(insn, 0, 5); + int rn = extract32(insn, 5, 5); + int imm4 = extract32(insn, 11, 4); + int imm5 = extract32(insn, 16, 5); + int op = extract32(insn, 29, 1); + + if (op != 0 || imm4 != 0) { + unallocated_encoding(s); + return; + } + + /* DUP (element, scalar) */ + handle_simd_dupes(s, rd, rn, imm5); } /* C3.6.8 AdvSIMD scalar pairwise -- 1.8.5