From: Peter Maydell <peter.maydell@linaro.org>
To: Anthony Liguori <aliguori@amazon.com>
Cc: Blue Swirl <blauwirbel@gmail.com>,
qemu-devel@nongnu.org, Aurelien Jarno <aurelien@aurel32.net>
Subject: [Qemu-devel] [PULL 26/38] target-arm: A64: Add SIMD three-different ABDL instructions
Date: Wed, 29 Jan 2014 13:39:53 +0000 [thread overview]
Message-ID: <1391002805-26596-27-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1391002805-26596-1-git-send-email-peter.maydell@linaro.org>
Implement the absolute-difference instructions in the SIMD
three-different group: SABAL, SABAL2, UABAL, UABAL2, SABDL,
SABDL2, UABDL, UABDL2.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
---
target-arm/translate-a64.c | 35 +++++++++++++++++++++++++++++++++--
1 file changed, 33 insertions(+), 2 deletions(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index e8479a5..e098efd 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -5602,6 +5602,21 @@ static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size,
}
switch (opcode) {
+ case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
+ case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
+ {
+ TCGv_i64 tcg_tmp1 = tcg_temp_new_i64();
+ TCGv_i64 tcg_tmp2 = tcg_temp_new_i64();
+
+ tcg_gen_sub_i64(tcg_tmp1, tcg_op1, tcg_op2);
+ tcg_gen_sub_i64(tcg_tmp2, tcg_op2, tcg_op1);
+ tcg_gen_movcond_i64(is_u ? TCG_COND_GEU : TCG_COND_GE,
+ tcg_passres,
+ tcg_op1, tcg_op2, tcg_tmp1, tcg_tmp2);
+ tcg_temp_free_i64(tcg_tmp1);
+ tcg_temp_free_i64(tcg_tmp2);
+ break;
+ }
case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
@@ -5640,6 +5655,22 @@ static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size,
}
switch (opcode) {
+ case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
+ case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
+ if (size == 0) {
+ if (is_u) {
+ gen_helper_neon_abdl_u16(tcg_passres, tcg_op1, tcg_op2);
+ } else {
+ gen_helper_neon_abdl_s16(tcg_passres, tcg_op1, tcg_op2);
+ }
+ } else {
+ if (is_u) {
+ gen_helper_neon_abdl_u32(tcg_passres, tcg_op1, tcg_op2);
+ } else {
+ gen_helper_neon_abdl_s32(tcg_passres, tcg_op1, tcg_op2);
+ }
+ }
+ break;
case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
@@ -5739,10 +5770,10 @@ static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn)
/* fall through */
case 0:
case 2:
- case 5:
- case 7:
unsupported_encoding(s, insn);
break;
+ case 5:
+ case 7:
case 8:
case 10:
case 12:
--
1.8.5
next prev parent reply other threads:[~2014-01-29 13:40 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-01-29 13:39 [Qemu-devel] [PULL 00/38] target-arm queue Peter Maydell
2014-01-29 13:39 ` [Qemu-devel] [PULL 01/38] target-arm: A64: Add SIMD ld/st multiple Peter Maydell
2014-01-29 13:39 ` [Qemu-devel] [PULL 02/38] target-arm: A64: Add SIMD ld/st single Peter Maydell
2014-01-29 13:39 ` [Qemu-devel] [PULL 03/38] target-arm: A64: Add decode skeleton for SIMD data processing insns Peter Maydell
2014-01-29 13:39 ` [Qemu-devel] [PULL 04/38] target-arm: A64: Add SIMD EXT Peter Maydell
2014-01-29 13:39 ` [Qemu-devel] [PULL 05/38] target-arm: A64: Add SIMD TBL/TBLX Peter Maydell
2014-01-29 13:39 ` [Qemu-devel] [PULL 06/38] target-arm: A64: Add SIMD ZIP/UZP/TRN Peter Maydell
2014-01-29 13:39 ` [Qemu-devel] [PULL 07/38] target-arm: A64: Add SIMD across-lanes instructions Peter Maydell
2014-01-29 13:39 ` [Qemu-devel] [PULL 08/38] target-arm: A64: Add SIMD copy operations Peter Maydell
2014-01-29 13:39 ` [Qemu-devel] [PULL 09/38] target-arm: A64: Add SIMD modified immediate group Peter Maydell
2014-01-29 13:39 ` [Qemu-devel] [PULL 10/38] target-arm: A64: Add SIMD scalar copy instructions Peter Maydell
2014-01-29 13:39 ` [Qemu-devel] [PULL 11/38] hw/arm/boot: Don't set up ATAGS for autogenerated dtb booting Peter Maydell
2014-01-29 13:39 ` [Qemu-devel] [PULL 12/38] ARM: Convert MIDR to a property Peter Maydell
2014-01-29 13:39 ` [Qemu-devel] [PULL 13/38] ZYNQ: Implement board MIDR control for Zynq Peter Maydell
2014-01-29 13:39 ` [Qemu-devel] [PULL 14/38] display: avoid multi-statement macro Peter Maydell
2014-01-29 13:39 ` [Qemu-devel] [PULL 15/38] target-arm: Move arm_rmode_to_sf to a shared location Peter Maydell
2014-01-29 13:39 ` [Qemu-devel] [PULL 16/38] target-arm: Add AArch32 FP VRINTA, VRINTN, VRINTP and VRINTM Peter Maydell
2014-01-29 13:39 ` [Qemu-devel] [PULL 17/38] target-arm: Add support for AArch32 FP VRINTR Peter Maydell
2014-01-29 13:39 ` [Qemu-devel] [PULL 18/38] target-arm: Add support for AArch32 FP VRINTZ Peter Maydell
2014-01-29 13:39 ` [Qemu-devel] [PULL 19/38] target-arm: Add support for AArch32 FP VRINTX Peter Maydell
2014-01-29 13:39 ` [Qemu-devel] [PULL 20/38] target-arm: Add support for AArch32 SIMD VRINTX Peter Maydell
2014-01-29 13:39 ` [Qemu-devel] [PULL 21/38] target-arm: Add set_neon_rmode helper Peter Maydell
2014-01-29 13:39 ` [Qemu-devel] [PULL 22/38] target-arm: Add AArch32 SIMD VRINTA, VRINTN, VRINTP, VRINTM, VRINTZ Peter Maydell
2014-01-29 13:39 ` [Qemu-devel] [PULL 23/38] target-arm: Add AArch32 FP VCVTA, VCVTN, VCVTP and VCVTM Peter Maydell
2014-01-29 13:39 ` [Qemu-devel] [PULL 24/38] target-arm: Add AArch32 SIMD " Peter Maydell
2014-01-29 13:39 ` [Qemu-devel] [PULL 25/38] target-arm: A64: Add SIMD three-different multiply accumulate insns Peter Maydell
2014-01-29 13:39 ` Peter Maydell [this message]
2014-01-29 13:39 ` [Qemu-devel] [PULL 27/38] target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops Peter Maydell
2014-01-29 13:39 ` [Qemu-devel] [PULL 28/38] target-arm: A64: Add top level decode for SIMD 3-same group Peter Maydell
2014-01-29 13:39 ` [Qemu-devel] [PULL 29/38] target-arm: A64: Add logic ops from SIMD 3 same group Peter Maydell
2014-01-29 13:39 ` [Qemu-devel] [PULL 30/38] target-arm: A64: Add integer ops from SIMD 3-same group Peter Maydell
2014-01-29 13:39 ` [Qemu-devel] [PULL 31/38] target-arm: A64: Add simple SIMD 3-same floating point ops Peter Maydell
2014-01-29 13:39 ` [Qemu-devel] [PULL 32/38] target-arm: A64: Add SIMD shift by immediate Peter Maydell
2014-01-29 13:40 ` [Qemu-devel] [PULL 33/38] linux-headers: Update from Linus' master ba635f8 Peter Maydell
2014-01-29 13:40 ` [Qemu-devel] [PULL 34/38] kvm: Introduce kvm_arch_irqchip_create Peter Maydell
2014-01-29 13:40 ` [Qemu-devel] [PULL 35/38] kvm: Common device control API functions Peter Maydell
2014-01-29 13:40 ` [Qemu-devel] [PULL 36/38] arm: vgic device control api support Peter Maydell
2014-01-29 13:40 ` [Qemu-devel] [PULL 37/38] arm_gic: Introduce define for GIC_NR_SGIS Peter Maydell
2014-01-29 13:40 ` [Qemu-devel] [PULL 38/38] arm_gic: Fix GICD_ICPENDR and GICD_ISPENDR writes Peter Maydell
2014-01-31 14:36 ` [Qemu-devel] [PULL 00/38] target-arm queue Peter Maydell
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