From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38778) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W9GUV-0000Az-Mt for qemu-devel@nongnu.org; Fri, 31 Jan 2014 10:58:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W9GUU-0005SL-CI for qemu-devel@nongnu.org; Fri, 31 Jan 2014 10:58:51 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:45421) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W9GUU-0005Pb-1f for qemu-devel@nongnu.org; Fri, 31 Jan 2014 10:58:50 -0500 From: Peter Maydell Date: Fri, 31 Jan 2014 15:45:28 +0000 Message-Id: <1391183143-30724-21-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1391183143-30724-1-git-send-email-peter.maydell@linaro.org> References: <1391183143-30724-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH v2 20/35] target-arm: Implement AArch64 CurrentEL sysreg List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Rob Herring , Peter Crosthwaite , patches@linaro.org, Michael Matz , Alexander Graf , Claudio Fontana , Dirk Mueller , Will Newton , Laurent Desnogues , =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvmarm@lists.cs.columbia.edu, Christoffer Dall , Richard Henderson Implement the CurrentEL sysreg. Signed-off-by: Peter Maydell --- target-arm/cpu.h | 3 ++- target-arm/helper.c | 3 +++ target-arm/translate-a64.c | 7 +++++++ 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index f5b706e..e0e3736 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -732,7 +732,8 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8)) #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8)) #define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8)) -#define ARM_LAST_SPECIAL ARM_CP_NZCV +#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8)) +#define ARM_LAST_SPECIAL ARM_CP_CURRENTEL /* Used only as a terminator for ARMCPRegInfo lists */ #define ARM_CP_SENTINEL 0xffff /* Mask of only the flag bits in a type field */ diff --git a/target-arm/helper.c b/target-arm/helper.c index f46dd0f..0538f78 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1533,6 +1533,9 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0, .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0x10 }, + { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2, + .access = PL1_R, .type = ARM_CP_CURRENTEL }, REGINFO_SENTINEL }; diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index f437359..fa8d7ac 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -1233,6 +1233,13 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, gen_set_nzcv(tcg_rt); } return; + case ARM_CP_CURRENTEL: + /* Reads as current EL value from pstate, which is + * guaranteed to be constant by the tb flags. + */ + tcg_rt = cpu_reg(s, rt); + tcg_gen_movi_i64(tcg_rt, s->current_pl << 2); + return; default: break; } -- 1.8.5