From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Rob Herring" <rob.herring@linaro.org>,
"Peter Crosthwaite" <peter.crosthwaite@xilinx.com>,
patches@linaro.org, "Michael Matz" <matz@suse.de>,
"Alexander Graf" <agraf@suse.de>,
"Claudio Fontana" <claudio.fontana@linaro.org>,
"Dirk Mueller" <dmueller@suse.de>,
"Will Newton" <will.newton@linaro.org>,
"Laurent Desnogues" <laurent.desnogues@gmail.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
kvmarm@lists.cs.columbia.edu,
"Christoffer Dall" <christoffer.dall@linaro.org>,
"Richard Henderson" <rth@twiddle.net>
Subject: [Qemu-devel] [PATCH v2 06/35] target-arm: Log bad system register accesses with LOG_UNIMP
Date: Fri, 31 Jan 2014 15:45:14 +0000 [thread overview]
Message-ID: <1391183143-30724-7-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1391183143-30724-1-git-send-email-peter.maydell@linaro.org>
Log guest attempts to access unimplemented system registers via
the LOG_UNIMP reporting mechanism (for both the 32 bit and 64 bit
instruction sets). This is particularly useful for debugging
problems where the guest is trying to use a system register that
QEMU doesn't implement.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---
target-arm/translate-a64.c | 7 ++++++-
target-arm/translate.c | 13 +++++++++++++
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index ee768f2..f808998 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -1172,7 +1172,12 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
crn, crm, op0, op1, op2));
if (!ri) {
- /* Unknown register */
+ /* Unknown register; this might be a guest error or a QEMU
+ * unimplemented feature.
+ */
+ qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch64 "
+ "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
+ isread ? "read" : "write", op0, op1, crn, crm, op2);
unallocated_encoding(s);
return;
}
diff --git a/target-arm/translate.c b/target-arm/translate.c
index e701c0f..45886f9 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -6923,6 +6923,19 @@ static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
return 0;
}
+ /* Unknown register; this might be a guest error or a QEMU
+ * unimplemented feature.
+ */
+ if (is64) {
+ qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch32 "
+ "64 bit system register cp:%d opc1: %d crm:%d\n",
+ isread ? "read" : "write", cpnum, opc1, crm);
+ } else {
+ qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch32 "
+ "system register cp:%d opc1:%d crn:%d crm:%d opc2:%d\n",
+ isread ? "read" : "write", cpnum, opc1, crn, crm, opc2);
+ }
+
return 1;
}
--
1.8.5
next prev parent reply other threads:[~2014-01-31 15:58 UTC|newest]
Thread overview: 83+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-01-31 15:45 [Qemu-devel] [PATCH v2 00/35] AArch64 system mode: system register rework Peter Maydell
2014-01-31 15:45 ` [Qemu-devel] [PATCH v2 01/35] target-arm: Fix raw read and write functions on AArch64 registers Peter Maydell
2014-01-31 15:56 ` Rob Herring
2014-01-31 16:06 ` Peter Maydell
2014-01-31 16:38 ` Peter Maydell
2014-01-31 15:45 ` [Qemu-devel] [PATCH v2 02/35] target-arm/kvm-consts.h: Define QEMU constants for known KVM CPUs Peter Maydell
2014-01-31 15:45 ` [Qemu-devel] [PATCH v2 03/35] target-arm: Define names for SCTLR bits Peter Maydell
2014-01-31 15:45 ` [Qemu-devel] [PATCH v2 04/35] target-arm: Restrict check_ap() use of S and R bits to v6 and earlier Peter Maydell
2014-01-31 15:45 ` [Qemu-devel] [PATCH v2 05/35] target-arm: Remove unused ARMCPUState sr substruct Peter Maydell
2014-02-05 6:03 ` Peter Crosthwaite
2014-01-31 15:45 ` Peter Maydell [this message]
2014-01-31 15:45 ` [Qemu-devel] [PATCH v2 07/35] target-arm: Add exception level to the AArch64 TB flags Peter Maydell
2014-01-31 15:45 ` [Qemu-devel] [PATCH v2 08/35] target-arm: A64: Implement store-exclusive for system mode Peter Maydell
2014-02-11 18:43 ` Peter Maydell
2014-01-31 15:45 ` [Qemu-devel] [PATCH v2 09/35] target-arm: A64: Implement MSR (immediate) instructions Peter Maydell
2014-02-05 6:23 ` Peter Crosthwaite
2014-02-05 10:55 ` Peter Maydell
2014-02-14 16:41 ` Peter Maydell
2014-02-14 23:07 ` Peter Crosthwaite
2014-01-31 15:45 ` [Qemu-devel] [PATCH v2 10/35] target-arm: Stop underdecoding ARM946 PRBS registers Peter Maydell
2014-01-31 15:45 ` [Qemu-devel] [PATCH v2 11/35] target-arm: Split cpreg access checks out from read/write functions Peter Maydell
2014-02-09 2:50 ` Peter Crosthwaite
2014-02-09 12:02 ` Peter Maydell
2014-02-11 6:13 ` Peter Crosthwaite
2014-02-11 6:13 ` Peter Crosthwaite
2014-01-31 15:45 ` [Qemu-devel] [PATCH v2 12/35] target-arm: Convert performance monitor reginfo to accesfn Peter Maydell
2014-02-05 6:59 ` Peter Crosthwaite
2014-02-05 11:01 ` Peter Maydell
2014-02-06 0:05 ` Alistair Francis
2014-02-09 2:59 ` Peter Crosthwaite
2014-02-09 12:04 ` Peter Maydell
2014-01-31 15:45 ` [Qemu-devel] [PATCH v2 13/35] target-arm: Convert generic timer reginfo to accessfn Peter Maydell
2014-02-09 3:05 ` Peter Crosthwaite
2014-01-31 15:45 ` [Qemu-devel] [PATCH v2 14/35] target-arm: Convert miscellaneous reginfo structs " Peter Maydell
2014-02-09 3:09 ` Peter Crosthwaite
2014-02-09 12:09 ` Peter Maydell
2014-01-31 15:45 ` [Qemu-devel] [PATCH v2 15/35] target-arm: Drop success/fail return from cpreg read and write functions Peter Maydell
2014-02-09 3:27 ` Peter Crosthwaite
2014-02-09 12:15 ` Peter Maydell
2014-01-31 15:45 ` [Qemu-devel] [PATCH v2 16/35] target-arm: Remove unnecessary code now read/write fns can't fail Peter Maydell
2014-02-09 3:29 ` Peter Crosthwaite
2014-01-31 15:45 ` [Qemu-devel] [PATCH v2 17/35] target-arm: Remove failure status return from read/write_raw_cp_reg Peter Maydell
2014-02-09 3:32 ` Peter Crosthwaite
2014-01-31 15:45 ` [Qemu-devel] [PATCH v2 18/35] target-arm: Fix incorrect type for value argument to write_raw_cp_reg Peter Maydell
2014-02-05 7:07 ` Peter Crosthwaite
2014-01-31 15:45 ` [Qemu-devel] [PATCH v2 19/35] target-arm: A64: Make cache ID registers visible to AArch64 Peter Maydell
2014-02-07 7:35 ` Hu Tao
2014-02-07 10:27 ` Peter Maydell
2014-02-11 8:38 ` Hu Tao
2014-02-09 2:15 ` Peter Crosthwaite
2014-02-09 11:52 ` Peter Maydell
2014-02-09 21:01 ` Peter Crosthwaite
2014-01-31 15:45 ` [Qemu-devel] [PATCH v2 20/35] target-arm: Implement AArch64 CurrentEL sysreg Peter Maydell
2014-02-09 2:17 ` Peter Crosthwaite
2014-01-31 15:45 ` [Qemu-devel] [PATCH v2 21/35] target-arm: Implement AArch64 MIDR_EL1 Peter Maydell
2014-01-31 15:45 ` [Qemu-devel] [PATCH v2 22/35] target-arm: Implement AArch64 DAIF system register Peter Maydell
2014-02-09 2:20 ` Peter Crosthwaite
2014-01-31 15:45 ` [Qemu-devel] [PATCH v2 23/35] target-arm: Implement AArch64 cache invalidate/clean ops Peter Maydell
2014-02-06 11:45 ` Peter Maydell
2014-02-09 2:22 ` Peter Crosthwaite
2014-01-31 15:45 ` [Qemu-devel] [PATCH v2 24/35] target-arm: Implement AArch64 TLB invalidate ops Peter Maydell
2014-01-31 15:45 ` [Qemu-devel] [PATCH v2 25/35] target-arm: Implement AArch64 dummy MDSCR_EL1 Peter Maydell
2014-02-09 2:27 ` Peter Crosthwaite
2014-01-31 15:45 ` [Qemu-devel] [PATCH v2 26/35] target-arm: Implement AArch64 memory attribute registers Peter Maydell
2014-02-09 2:31 ` Peter Crosthwaite
2014-01-31 15:45 ` [Qemu-devel] [PATCH v2 27/35] target-arm: Implement AArch64 SCTLR_EL1 Peter Maydell
2014-02-09 2:32 ` Peter Crosthwaite
2014-01-31 15:45 ` [Qemu-devel] [PATCH v2 28/35] target-arm: Implement AArch64 TCR_EL1 Peter Maydell
2014-02-09 2:35 ` Peter Crosthwaite
2014-01-31 15:45 ` [Qemu-devel] [PATCH v2 29/35] target-arm: Implement AArch64 VBAR_EL1 Peter Maydell
2014-01-31 15:45 ` [Qemu-devel] [PATCH v2 30/35] target-arm: Implement AArch64 TTBR* Peter Maydell
2014-02-09 2:38 ` Peter Crosthwaite
2014-01-31 15:45 ` [Qemu-devel] [PATCH v2 31/35] target-arm: Implement AArch64 MPIDR Peter Maydell
2014-01-31 15:45 ` [Qemu-devel] [PATCH v2 32/35] target-arm: Implement AArch64 generic timers Peter Maydell
2014-01-31 15:45 ` [Qemu-devel] [PATCH v2 33/35] target-arm: Implement AArch64 ID and feature registers Peter Maydell
2014-02-09 2:42 ` Peter Crosthwaite
2014-01-31 15:45 ` [Qemu-devel] [PATCH v2 34/35] target-arm: Implement AArch64 dummy breakpoint and watchpoint registers Peter Maydell
2014-02-09 2:44 ` Peter Crosthwaite
2014-01-31 15:45 ` [Qemu-devel] [PATCH v2 35/35] target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI Peter Maydell
2014-02-09 2:44 ` Peter Crosthwaite
2014-02-11 6:11 ` [Qemu-devel] [PATCH v2 00/35] AArch64 system mode: system register rework Peter Crosthwaite
2014-02-11 9:05 ` Peter Maydell
2014-02-11 17:12 ` Peter Maydell
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