From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35777) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W9GHx-0004wM-82 for qemu-devel@nongnu.org; Fri, 31 Jan 2014 10:45:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W9GHs-0001gE-RS for qemu-devel@nongnu.org; Fri, 31 Jan 2014 10:45:53 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:45333) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W9GHs-0001g2-KS for qemu-devel@nongnu.org; Fri, 31 Jan 2014 10:45:48 -0500 From: Peter Maydell Date: Fri, 31 Jan 2014 15:45:15 +0000 Message-Id: <1391183143-30724-8-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1391183143-30724-1-git-send-email-peter.maydell@linaro.org> References: <1391183143-30724-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH v2 07/35] target-arm: Add exception level to the AArch64 TB flags List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Rob Herring , Peter Crosthwaite , patches@linaro.org, Michael Matz , Alexander Graf , Claudio Fontana , Dirk Mueller , Will Newton , Laurent Desnogues , =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvmarm@lists.cs.columbia.edu, Christoffer Dall , Richard Henderson We already implicitly rely on the exception level being part of the TB flags for coprocessor access, so actually include it. (This makes no difference for linux-user mode, which is always in EL0, but will be needed for correct operation in system emulation.) Signed-off-by: Peter Maydell --- target-arm/cpu.h | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 70cd5a0..385cfcd 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -1056,7 +1056,9 @@ static inline int cpu_mmu_index (CPUARMState *env) #define ARM_TBFLAG_BSWAP_CODE_SHIFT 16 #define ARM_TBFLAG_BSWAP_CODE_MASK (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT) -/* Bit usage when in AArch64 state: currently no bits defined */ +/* Bit usage when in AArch64 state */ +#define ARM_TBFLAG_AA64_EL_SHIFT 0 +#define ARM_TBFLAG_AA64_EL_MASK (0x3 << ARM_TBFLAG_AA64_EL_SHIFT) /* some convenience accessor macros */ #define ARM_TBFLAG_AARCH64_STATE(F) \ @@ -1075,13 +1077,16 @@ static inline int cpu_mmu_index (CPUARMState *env) (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT) #define ARM_TBFLAG_BSWAP_CODE(F) \ (((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT) +#define ARM_TBFLAG_AA64_EL(F) \ + (((F) & ARM_TBFLAG_AA64_EL_MASK) >> ARM_TBFLAG_AA64_EL_SHIFT) static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, int *flags) { if (is_a64(env)) { *pc = env->pc; - *flags = ARM_TBFLAG_AARCH64_STATE_MASK; + *flags = ARM_TBFLAG_AARCH64_STATE_MASK + | arm_current_pl(env) << ARM_TBFLAG_AA64_EL_SHIFT; } else { int privmode; *pc = env->regs[15]; -- 1.8.5