[Qemu-devel] [V2 PATCH 0/9] target-ppc: Base ISA V2.07 for Power8

[Tom Musta <tommusta@gmail.com>]

This patch series adds the branch and integer instructions that were 
introduced in Power ISA 2.07.  Specifically,

  - There is a new conditional Branch to Address Register (bctar) instruction.
  - The load/store quadword instructions are now supported in user mode (Book I).
  - Quadword atomic instructions have been added (lqarx, stqcx.).

ISA 2.07 additions for other categories (VSX, Altivec, Decimal Floating Point,
transactional memory) are not included in this patch series; they will be 
contributed via other patches.

V2: Addressing review comments from Alex Graf:
    (1) Refactored user-mode and Little Endian checks in the load and store
        quadword instructions.
    (2) Added reserve_val2 element to CPU state in support of quadword atomic
        instructions.

Tom Musta (9):
  target-ppc: Add Flag for bctar
  target-ppc: Add Target Address SPR (TAR) to Power8
  target-ppc: Add bctar Instruction
  target-ppc: Add Flag for ISA 2.07 Load/Store Quadword Instructions
  target-ppc: Add is_user_mode Utility Routine
  target-ppc: Load Quadword
  target-ppc: Store Quadword
  target-ppc: Add Load Quadword and Reserve
  target-ppc: Add Store Quadword Conditional

 linux-user/main.c           |   18 +++++-
 target-ppc/cpu.h            |   10 ++-
 target-ppc/translate.c      |  160 ++++++++++++++++++++++++++++++++++---------
 target-ppc/translate_init.c |   19 ++++-
 4 files changed, 168 insertions(+), 39 deletions(-)