From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49813) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W9nMt-0006il-L3 for qemu-devel@nongnu.org; Sat, 01 Feb 2014 22:05:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W9nMm-0003DG-Ar for qemu-devel@nongnu.org; Sat, 01 Feb 2014 22:05:11 -0500 Received: from mail-pb0-x22f.google.com ([2607:f8b0:400e:c01::22f]:37339) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W9nMm-0003Aj-4j for qemu-devel@nongnu.org; Sat, 01 Feb 2014 22:05:04 -0500 Received: by mail-pb0-f47.google.com with SMTP id rp16so5836495pbb.34 for ; Sat, 01 Feb 2014 19:05:03 -0800 (PST) Received: from localhost (ec2-54-206-39-244.ap-southeast-2.compute.amazonaws.com. [54.206.39.244]) by mx.google.com with ESMTPSA id oa3sm42198176pbb.15.2014.02.01.19.05.02 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Sat, 01 Feb 2014 19:05:02 -0800 (PST) From: edgar.iglesias@gmail.com Date: Sun, 2 Feb 2014 03:04:49 +0000 Message-Id: <1391310292-18008-4-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1391310292-18008-1-git-send-email-edgar.iglesias@gmail.com> References: <1391310292-18008-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH 3/6] cris: Add interrupt signals to the CPU device List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias --- target-cris/cpu.c | 20 ++++++++++++++++++++ target-cris/cpu.h | 4 ++++ 2 files changed, 24 insertions(+) diff --git a/target-cris/cpu.c b/target-cris/cpu.c index 21f1860..7dea0f0 100644 --- a/target-cris/cpu.c +++ b/target-cris/cpu.c @@ -146,6 +146,21 @@ static void cris_cpu_realizefn(DeviceState *dev, Error **errp) ccc->parent_realize(dev, errp); } +#ifndef CONFIG_USER_ONLY +static void cris_cpu_set_irq(void *opaque, int irq, int level) +{ + CRISCPU *cpu = opaque; + CPUState *cs = CPU(cpu); + int type = irq == CRIS_CPU_IRQ ? CPU_INTERRUPT_HARD : CPU_INTERRUPT_NMI; + + if (level) { + cpu_interrupt(cs, type); + } else { + cpu_reset_interrupt(cs, type); + } +} +#endif + static void cris_cpu_initfn(Object *obj) { CPUState *cs = CPU(obj); @@ -159,6 +174,11 @@ static void cris_cpu_initfn(Object *obj) env->pregs[PR_VR] = ccc->vr; +#ifndef CONFIG_USER_ONLY + /* IRQ and NMI lines. */ + qdev_init_gpio_in(DEVICE(cpu), cris_cpu_set_irq, 2); +#endif + if (tcg_enabled() && !tcg_initialized) { tcg_initialized = true; if (env->pregs[PR_VR] < 32) { diff --git a/target-cris/cpu.h b/target-cris/cpu.h index 4b9fc4c..1d7d80d 100644 --- a/target-cris/cpu.h +++ b/target-cris/cpu.h @@ -42,6 +42,10 @@ /* CRIS-specific interrupt pending bits. */ #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 +/* CRUS CPU device objects interrupt lines. */ +#define CRIS_CPU_IRQ 0 +#define CRIS_CPU_NMI 1 + /* Register aliases. R0 - R15 */ #define R_FP 8 #define R_SP 14 -- 1.8.3.2