From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47261) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WCAIX-0007dQ-7I for qemu-devel@nongnu.org; Sat, 08 Feb 2014 10:58:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WCAIW-0002xy-Ao for qemu-devel@nongnu.org; Sat, 08 Feb 2014 10:58:29 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:45684) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WCAIW-0002tl-4K for qemu-devel@nongnu.org; Sat, 08 Feb 2014 10:58:28 -0500 From: Peter Maydell Date: Sat, 8 Feb 2014 15:57:48 +0000 Message-Id: <1391875084-12772-14-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1391875084-12772-1-git-send-email-peter.maydell@linaro.org> References: <1391875084-12772-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 13/29] target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc group List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anthony Liguori Cc: Blue Swirl , qemu-devel@nongnu.org, Aurelien Jarno Add the SIMD FNEG and FABS instructions in the SIMD 2-reg-misc group. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target-arm/translate-a64.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index a941c48..5698b3e 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -6219,7 +6219,7 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u, { /* Handle 64->64 opcodes which are shared between the scalar and * vector 2-reg-misc groups. We cover every integer opcode where size == 3 - * is valid in either group. + * is valid in either group and also the double-precision fp ops. */ TCGCond cond; @@ -6257,6 +6257,12 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u, tcg_temp_free_i64(tcg_zero); } break; + case 0x2f: /* FABS */ + gen_helper_vfp_absd(tcg_rd, tcg_rn); + break; + case 0x6f: /* FNEG */ + gen_helper_vfp_negd(tcg_rd, tcg_rn); + break; default: g_assert_not_reached(); } @@ -7605,6 +7611,13 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) opcode |= (extract32(size, 1, 1) << 5) | (u << 6); size = extract32(size, 0, 1) ? 3 : 2; switch (opcode) { + case 0x2f: /* FABS */ + case 0x6f: /* FNEG */ + if (size == 3 && !is_q) { + unallocated_encoding(s); + return; + } + break; case 0x16: /* FCVTN, FCVTN2 */ case 0x17: /* FCVTL, FCVTL2 */ case 0x18: /* FRINTN */ @@ -7616,7 +7629,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) case 0x2c: /* FCMGT (zero) */ case 0x2d: /* FCMEQ (zero) */ case 0x2e: /* FCMLT (zero) */ - case 0x2f: /* FABS */ case 0x38: /* FRINTP */ case 0x39: /* FRINTZ */ case 0x3a: /* FCVTPS */ @@ -7632,7 +7644,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) case 0x5d: /* UCVTF */ case 0x6c: /* FCMGE (zero) */ case 0x6d: /* FCMLE (zero) */ - case 0x6f: /* FNEG */ case 0x79: /* FRINTI */ case 0x7a: /* FCVTPU */ case 0x7b: /* FCVTZU */ @@ -7709,6 +7720,12 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) tcg_temp_free_i32(tcg_zero); } break; + case 0x2f: /* FABS */ + gen_helper_vfp_abss(tcg_res, tcg_op); + break; + case 0x6f: /* FNEG */ + gen_helper_vfp_negs(tcg_res, tcg_op); + break; default: g_assert_not_reached(); } -- 1.8.5