From: Peter Maydell <peter.maydell@linaro.org>
To: Anthony Liguori <aliguori@amazon.com>
Cc: Blue Swirl <blauwirbel@gmail.com>,
	qemu-devel@nongnu.org, Aurelien Jarno <aurelien@aurel32.net>
Subject: [Qemu-devel] [PULL 29/29] arm/zynq: Add software system reset via SCLR
Date: Sat,  8 Feb 2014 15:58:04 +0000	[thread overview]
Message-ID: <1391875084-12772-30-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1391875084-12772-1-git-send-email-peter.maydell@linaro.org>
From: Sebastian Huber <sebastian.huber@embedded-brains.de>
Support software-driven system reset via the register in the SCLR.
Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/misc/zynq_slcr.c | 5 +++++
 1 file changed, 5 insertions(+)
diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c
index e42a5b0..d1cc233 100644
--- a/hw/misc/zynq_slcr.c
+++ b/hw/misc/zynq_slcr.c
@@ -31,6 +31,8 @@
 #define XILINX_LOCK_KEY 0x767b
 #define XILINX_UNLOCK_KEY 0xdf0d
 
+#define R_PSS_RST_CTRL_SOFT_RST 0x1
+
 typedef enum {
   ARM_PLL_CTRL,
   DDR_PLL_CTRL,
@@ -399,6 +401,9 @@ static void zynq_slcr_write(void *opaque, hwaddr offset,
                 goto bad_reg;
             }
             s->reset[(offset - 0x200) / 4] = val;
+            if (offset == 0x200 && (val & R_PSS_RST_CTRL_SOFT_RST)) {
+                qemu_system_reset_request();
+            }
             break;
         case 0x300:
             s->apu_ctrl = val;
-- 
1.8.5
next prev parent reply	other threads:[~2014-02-08 15:58 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-02-08 15:57 [Qemu-devel] [PULL 00/29] target-arm queue Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 01/29] target-arm: A64: Implement SIMD 3-reg-same shift and saturate insns Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 02/29] target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insns Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 03/29] target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMD Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 04/29] tcg: Add TCGV_UNUSED_PTR, TCGV_IS_UNUSED_PTR, TCGV_EQUAL_PTR Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 05/29] target-arm: A64: Implement scalar pairwise ops Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 06/29] target-arm: A64: Implement remaining integer scalar-3-same insns Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 07/29] target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg misc Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 08/29] target-arm: A64: Add skeleton decode for SIMD 2-reg misc group Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 09/29] target-arm: A64: Implement 2-register misc compares, ABS, NEG Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 10/29] target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 11/29] target-arm: A64: Add narrowing 2-reg-misc instructions Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 12/29] target-arm: A64: Add 2-reg-misc REV* instructions Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 13/29] target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc group Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 14/29] target-arm: Add support for AArch32 64bit VCVTB and VCVTT Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 15/29] arm_gic: Fix GIC pending behavior Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 16/29] arm_gic: Keep track of SGI sources Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 17/29] arm_gic: Support setting/getting binary point reg Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 18/29] vmstate: Add uint32 2D-array support Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 19/29] arm_gic: Add GICC_APRn state to the GICState Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 20/29] rules.mak: Support .cc as a C++ source file suffix Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 21/29] rules.mak: Link with C++ if we have a C++ compiler Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 22/29] disas: Add subset of libvixl sources for A64 disassembler Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 23/29] disas/libvixl: Fix upstream libvixl compilation issues Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 24/29] disas: Implement disassembly output for A64 Peter Maydell
2014-02-08 15:58 ` [Qemu-devel] [PULL 25/29] util/fifo8: implement push/pop of multiple bytes Peter Maydell
2014-02-08 15:58 ` [Qemu-devel] [PULL 26/29] util/fifo8: clear fifo head upon reset Peter Maydell
2014-02-08 15:58 ` [Qemu-devel] [PULL 27/29] hw/net: add support for Allwinner EMAC Fast Ethernet controller Peter Maydell
2014-02-08 15:58 ` [Qemu-devel] [PULL 28/29] hw/arm/allwinner-a10: initialize EMAC Peter Maydell
2014-02-08 15:58 ` Peter Maydell [this message]
2014-02-11 11:59 ` [Qemu-devel] [PULL 00/29] target-arm queue Peter Maydell
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