From: Tom Musta <tommusta@gmail.com>
To: qemu-devel@nongnu.org
Cc: Tom Musta <tommusta@gmail.com>, qemu-ppc@nongnu.org
Subject: [Qemu-devel] [V3 PATCH 3/9] target-ppc: Add bctar Instruction
Date: Mon, 10 Feb 2014 11:26:55 -0600 [thread overview]
Message-ID: <1392053222-7645-4-git-send-email-tommusta@gmail.com> (raw)
In-Reply-To: <1392053222-7645-1-git-send-email-tommusta@gmail.com>
This patch adds the Branch Conditional to Address Register (bctar)
instruction.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/translate.c | 11 ++++++++++-
1 files changed, 10 insertions(+), 1 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index d9abcca..b89b4ba 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -3745,6 +3745,7 @@ static void gen_b(DisasContext *ctx)
#define BCOND_IM 0
#define BCOND_LR 1
#define BCOND_CTR 2
+#define BCOND_TAR 3
static inline void gen_bcond(DisasContext *ctx, int type)
{
@@ -3753,10 +3754,12 @@ static inline void gen_bcond(DisasContext *ctx, int type)
TCGv target;
ctx->exception = POWERPC_EXCP_BRANCH;
- if (type == BCOND_LR || type == BCOND_CTR) {
+ if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
target = tcg_temp_local_new();
if (type == BCOND_CTR)
tcg_gen_mov_tl(target, cpu_ctr);
+ else if (type == BCOND_TAR)
+ gen_load_spr(target, SPR_TAR);
else
tcg_gen_mov_tl(target, cpu_lr);
} else {
@@ -3838,6 +3841,11 @@ static void gen_bclr(DisasContext *ctx)
gen_bcond(ctx, BCOND_LR);
}
+static void gen_bctar(DisasContext *ctx)
+{
+ gen_bcond(ctx, BCOND_TAR);
+}
+
/*** Condition register logical ***/
#define GEN_CRLOGIC(name, tcg_op, opc) \
static void glue(gen_, name)(DisasContext *ctx) \
@@ -9569,6 +9577,7 @@ GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
+GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
#if defined(TARGET_PPC64)
--
1.7.1
next prev parent reply other threads:[~2014-02-10 17:28 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-02-10 17:26 [Qemu-devel] [V3 PATCH 0/9] target-ppc: Base ISA V2.07 for Power8 Tom Musta
2014-02-10 17:26 ` [Qemu-devel] [V3 PATCH 1/9] target-ppc: Add Flag for bctar Tom Musta
2014-02-10 17:26 ` [Qemu-devel] [V3 PATCH 2/9] target-ppc: Add Target Address SPR (TAR) to Power8 Tom Musta
2014-02-10 17:26 ` Tom Musta [this message]
2014-02-10 17:26 ` [Qemu-devel] [V3 PATCH 4/9] target-ppc: Add Flag for ISA 2.07 Load/Store Quadword Instructions Tom Musta
2014-02-10 17:26 ` [Qemu-devel] [V3 PATCH 5/9] target-ppc: Add is_user_mode Utility Routine Tom Musta
2014-02-10 17:26 ` [Qemu-devel] [V3 PATCH 6/9] target-ppc: Load Quadword Tom Musta
2014-02-10 17:26 ` [Qemu-devel] [V3 PATCH 7/9] target-ppc: Store Quadword Tom Musta
2014-02-10 17:27 ` [Qemu-devel] [V3 PATCH 8/9] target-ppc: Add Load Quadword and Reserve Tom Musta
2014-02-10 17:27 ` [Qemu-devel] [V3 PATCH 9/9] target-ppc: Add Store Quadword Conditional Tom Musta
2014-02-20 14:20 ` [Qemu-devel] [Qemu-ppc] " Alexander Graf
2014-02-20 15:08 ` Alexander Graf
2014-02-20 15:00 ` [Qemu-devel] [Qemu-ppc] [V3 PATCH 0/9] target-ppc: Base ISA V2.07 for Power8 Alexander Graf
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