* [Qemu-devel] [PATCH 1/6] target-xtensa: add RRRI4 opcode format fields
2014-02-11 8:43 [Qemu-devel] [PATCH 0/6] target-xtensa: add basic checks to cache opcodes Max Filippov
@ 2014-02-11 8:43 ` Max Filippov
2014-02-11 8:43 ` [Qemu-devel] [PATCH 2/6] target-xtensa: add basic checks to dcache opcodes Max Filippov
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Max Filippov @ 2014-02-11 8:43 UTC (permalink / raw)
To: qemu-devel; +Cc: Max Filippov
This encoding is used by cache instructions.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
target-xtensa/translate.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index dc5e78f..b0b7fa0 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -922,6 +922,15 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
#define RRRN_S RRR_S
#define RRRN_T RRR_T
+#define RRI4_R RRR_R
+#define RRI4_S RRR_S
+#define RRI4_T RRR_T
+#ifdef TARGET_WORDS_BIGENDIAN
+#define RRI4_IMM4 ((b2) & 0xf)
+#else
+#define RRI4_IMM4 (((b2) & 0xf0) >> 4)
+#endif
+
#define RRI8_R RRR_R
#define RRI8_S RRR_S
#define RRI8_T RRR_T
--
1.8.1.4
^ permalink raw reply related [flat|nested] 7+ messages in thread* [Qemu-devel] [PATCH 2/6] target-xtensa: add basic checks to dcache opcodes
2014-02-11 8:43 [Qemu-devel] [PATCH 0/6] target-xtensa: add basic checks to cache opcodes Max Filippov
2014-02-11 8:43 ` [Qemu-devel] [PATCH 1/6] target-xtensa: add RRRI4 opcode format fields Max Filippov
@ 2014-02-11 8:43 ` Max Filippov
2014-02-11 8:43 ` [Qemu-devel] [PATCH 3/6] target-xtensa: add basic checks to icache opcodes Max Filippov
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Max Filippov @ 2014-02-11 8:43 UTC (permalink / raw)
To: qemu-devel; +Cc: Max Filippov
Check privilege level for privileged instructions (DHI, DHU, DII, DIU, DIWB,
DIWBI, DPFL are privileged), memory accessibility for instructions that
reference memory (all DH* and DPFL) and windowed register validity for all
data cache instructions.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
target-xtensa/translate.c | 38 ++++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index b0b7fa0..f08bcfe 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -2239,6 +2239,20 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
gen_load_store(st32, 2);
break;
+#define gen_dcache_hit_test(w, shift) do { \
+ TCGv_i32 addr = tcg_temp_new_i32(); \
+ TCGv_i32 res = tcg_temp_new_i32(); \
+ gen_window_check1(dc, RRI##w##_S); \
+ tcg_gen_addi_i32(addr, cpu_R[RRI##w##_S], \
+ RRI##w##_IMM##w << shift); \
+ tcg_gen_qemu_ld8u(res, addr, dc->cring); \
+ tcg_temp_free(addr); \
+ tcg_temp_free(res); \
+ } while (0)
+
+#define gen_dcache_hit_test4() gen_dcache_hit_test(4, 4)
+#define gen_dcache_hit_test8() gen_dcache_hit_test(8, 2)
+
case 7: /*CACHEc*/
if (RRI8_T < 8) {
HAS_OPTION(XTENSA_OPTION_DCACHE);
@@ -2246,49 +2260,69 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
switch (RRI8_T) {
case 0: /*DPFRc*/
+ gen_window_check1(dc, RRI8_S);
break;
case 1: /*DPFWc*/
+ gen_window_check1(dc, RRI8_S);
break;
case 2: /*DPFROc*/
+ gen_window_check1(dc, RRI8_S);
break;
case 3: /*DPFWOc*/
+ gen_window_check1(dc, RRI8_S);
break;
case 4: /*DHWBc*/
+ gen_dcache_hit_test8();
break;
case 5: /*DHWBIc*/
+ gen_dcache_hit_test8();
break;
case 6: /*DHIc*/
+ gen_check_privilege(dc);
+ gen_dcache_hit_test8();
break;
case 7: /*DIIc*/
+ gen_check_privilege(dc);
+ gen_window_check1(dc, RRI8_S);
break;
case 8: /*DCEc*/
switch (OP1) {
case 0: /*DPFLl*/
HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
+ gen_check_privilege(dc);
+ gen_dcache_hit_test4();
break;
case 2: /*DHUl*/
HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
+ gen_check_privilege(dc);
+ gen_dcache_hit_test4();
break;
case 3: /*DIUl*/
HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
+ gen_check_privilege(dc);
+ gen_window_check1(dc, RRI4_S);
break;
case 4: /*DIWBc*/
HAS_OPTION(XTENSA_OPTION_DCACHE);
+ gen_check_privilege(dc);
+ gen_window_check1(dc, RRI4_S);
break;
case 5: /*DIWBIc*/
HAS_OPTION(XTENSA_OPTION_DCACHE);
+ gen_check_privilege(dc);
+ gen_window_check1(dc, RRI4_S);
break;
default: /*reserved*/
@@ -2298,6 +2332,10 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
}
break;
+#undef gen_dcache_hit_test
+#undef gen_dcache_hit_test4
+#undef gen_dcache_hit_test8
+
case 12: /*IPFc*/
HAS_OPTION(XTENSA_OPTION_ICACHE);
break;
--
1.8.1.4
^ permalink raw reply related [flat|nested] 7+ messages in thread* [Qemu-devel] [PATCH 3/6] target-xtensa: add basic checks to icache opcodes
2014-02-11 8:43 [Qemu-devel] [PATCH 0/6] target-xtensa: add basic checks to cache opcodes Max Filippov
2014-02-11 8:43 ` [Qemu-devel] [PATCH 1/6] target-xtensa: add RRRI4 opcode format fields Max Filippov
2014-02-11 8:43 ` [Qemu-devel] [PATCH 2/6] target-xtensa: add basic checks to dcache opcodes Max Filippov
@ 2014-02-11 8:43 ` Max Filippov
2014-02-11 8:43 ` [Qemu-devel] [PATCH 4/6] target-xtensa: add overridable test_init macro Max Filippov
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Max Filippov @ 2014-02-11 8:43 UTC (permalink / raw)
To: qemu-devel; +Cc: Max Filippov
Check privilege level for privileged instructions (IHU, III, IIU and IPFL
are privileged), memory accessibility for instructions that reference memory
(IH* and IPFL) and windowed register validity for all instruction cache
instructions.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
target-xtensa/helper.h | 1 +
target-xtensa/op_helper.c | 5 +++++
target-xtensa/translate.c | 27 +++++++++++++++++++++++++++
3 files changed, 33 insertions(+)
diff --git a/target-xtensa/helper.h b/target-xtensa/helper.h
index 38d7157..322b04c 100644
--- a/target-xtensa/helper.h
+++ b/target-xtensa/helper.h
@@ -25,6 +25,7 @@ DEF_HELPER_2(advance_ccount, void, env, i32)
DEF_HELPER_1(check_interrupts, void, env)
DEF_HELPER_3(check_atomctl, void, env, i32, i32)
+DEF_HELPER_2(itlb_hit_test, void, env, i32)
DEF_HELPER_2(wsr_rasid, void, env, i32)
DEF_HELPER_FLAGS_3(rtlb0, TCG_CALL_NO_RWG_SE, i32, env, i32, i32)
DEF_HELPER_FLAGS_3(rtlb1, TCG_CALL_NO_RWG_SE, i32, env, i32, i32)
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index cf97025..c2dafd4 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -414,6 +414,11 @@ void HELPER(check_interrupts)(CPUXtensaState *env)
check_interrupts(env);
}
+void HELPER(itlb_hit_test)(CPUXtensaState *env, uint32_t vaddr)
+{
+ get_page_addr_code(env, vaddr);
+}
+
/*!
* Check vaddr accessibility/cache attributes and raise an exception if
* specified by the ATOMCTL SR.
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index f08bcfe..6061968 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -2336,22 +2336,42 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
#undef gen_dcache_hit_test4
#undef gen_dcache_hit_test8
+#define gen_icache_hit_test(w, shift) do { \
+ TCGv_i32 addr = tcg_temp_new_i32(); \
+ gen_window_check1(dc, RRI##w##_S); \
+ tcg_gen_movi_i32(cpu_pc, dc->pc); \
+ tcg_gen_addi_i32(addr, cpu_R[RRI##w##_S], \
+ RRI##w##_IMM##w << shift); \
+ gen_helper_itlb_hit_test(cpu_env, addr); \
+ tcg_temp_free(addr); \
+ } while (0)
+
+#define gen_icache_hit_test4() gen_icache_hit_test(4, 4)
+#define gen_icache_hit_test8() gen_icache_hit_test(8, 2)
+
case 12: /*IPFc*/
HAS_OPTION(XTENSA_OPTION_ICACHE);
+ gen_window_check1(dc, RRI8_S);
break;
case 13: /*ICEc*/
switch (OP1) {
case 0: /*IPFLl*/
HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
+ gen_check_privilege(dc);
+ gen_icache_hit_test4();
break;
case 2: /*IHUl*/
HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
+ gen_check_privilege(dc);
+ gen_icache_hit_test4();
break;
case 3: /*IIUl*/
HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
+ gen_check_privilege(dc);
+ gen_window_check1(dc, RRI4_S);
break;
default: /*reserved*/
@@ -2362,10 +2382,13 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
case 14: /*IHIc*/
HAS_OPTION(XTENSA_OPTION_ICACHE);
+ gen_icache_hit_test8();
break;
case 15: /*IIIc*/
HAS_OPTION(XTENSA_OPTION_ICACHE);
+ gen_check_privilege(dc);
+ gen_window_check1(dc, RRI8_S);
break;
default: /*reserved*/
@@ -2374,6 +2397,10 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
}
break;
+#undef gen_icache_hit_test
+#undef gen_icache_hit_test4
+#undef gen_icache_hit_test8
+
case 9: /*L16SI*/
gen_load_store(ld16s, 1);
break;
--
1.8.1.4
^ permalink raw reply related [flat|nested] 7+ messages in thread* [Qemu-devel] [PATCH 4/6] target-xtensa: add overridable test_init macro
2014-02-11 8:43 [Qemu-devel] [PATCH 0/6] target-xtensa: add basic checks to cache opcodes Max Filippov
` (2 preceding siblings ...)
2014-02-11 8:43 ` [Qemu-devel] [PATCH 3/6] target-xtensa: add basic checks to icache opcodes Max Filippov
@ 2014-02-11 8:43 ` Max Filippov
2014-02-11 8:43 ` [Qemu-devel] [PATCH 5/6] target-xtensa: allow using core configuration in tests Max Filippov
2014-02-11 8:43 ` [Qemu-devel] [PATCH 6/6] target-xtensa: add basic tests for cache opcodes Max Filippov
5 siblings, 0 replies; 7+ messages in thread
From: Max Filippov @ 2014-02-11 8:43 UTC (permalink / raw)
To: qemu-devel; +Cc: Max Filippov
Some test suites, like MMU, need per-test initialization. Don't make them
redefine test macro, add test_init for that purpose.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
tests/tcg/xtensa/macros.inc | 4 ++++
tests/tcg/xtensa/test_mmu.S | 4 ++--
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/tests/tcg/xtensa/macros.inc b/tests/tcg/xtensa/macros.inc
index c9be1ce..ead8528 100644
--- a/tests/tcg/xtensa/macros.inc
+++ b/tests/tcg/xtensa/macros.inc
@@ -43,8 +43,12 @@ main:
simcall
.endm
+.macro test_init
+.endm
+
.macro test name
//print test_\name
+ test_init
test_\name:
.global test_\name
.endm
diff --git a/tests/tcg/xtensa/test_mmu.S b/tests/tcg/xtensa/test_mmu.S
index 5d87fbb..4bc34e5 100644
--- a/tests/tcg/xtensa/test_mmu.S
+++ b/tests/tcg/xtensa/test_mmu.S
@@ -2,9 +2,9 @@
test_suite mmu
-.purgem test
+.purgem test_init
-.macro test name
+.macro test_init
movi a2, 0x00000004
idtlb a2
movi a2, 0x00100004
--
1.8.1.4
^ permalink raw reply related [flat|nested] 7+ messages in thread* [Qemu-devel] [PATCH 5/6] target-xtensa: allow using core configuration in tests
2014-02-11 8:43 [Qemu-devel] [PATCH 0/6] target-xtensa: add basic checks to cache opcodes Max Filippov
` (3 preceding siblings ...)
2014-02-11 8:43 ` [Qemu-devel] [PATCH 4/6] target-xtensa: add overridable test_init macro Max Filippov
@ 2014-02-11 8:43 ` Max Filippov
2014-02-11 8:43 ` [Qemu-devel] [PATCH 6/6] target-xtensa: add basic tests for cache opcodes Max Filippov
5 siblings, 0 replies; 7+ messages in thread
From: Max Filippov @ 2014-02-11 8:43 UTC (permalink / raw)
To: qemu-devel; +Cc: Max Filippov
Add path to the core configuration directory to test build command and
replace .include asm directive with #include to enable preprocessing.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
tests/tcg/xtensa/Makefile | 11 +++++++----
tests/tcg/xtensa/macros.inc | 2 ++
tests/tcg/xtensa/test_b.S | 2 +-
tests/tcg/xtensa/test_bi.S | 2 +-
tests/tcg/xtensa/test_boolean.S | 2 +-
tests/tcg/xtensa/test_break.S | 2 +-
tests/tcg/xtensa/test_bz.S | 2 +-
tests/tcg/xtensa/test_clamps.S | 2 +-
tests/tcg/xtensa/test_extui.S | 2 +-
tests/tcg/xtensa/test_fail.S | 2 +-
tests/tcg/xtensa/test_interrupt.S | 2 +-
tests/tcg/xtensa/test_loop.S | 2 +-
tests/tcg/xtensa/test_mac16.S | 2 +-
tests/tcg/xtensa/test_max.S | 2 +-
tests/tcg/xtensa/test_min.S | 2 +-
tests/tcg/xtensa/test_mmu.S | 2 +-
tests/tcg/xtensa/test_mul16.S | 2 +-
tests/tcg/xtensa/test_mul32.S | 2 +-
tests/tcg/xtensa/test_nsa.S | 2 +-
tests/tcg/xtensa/test_pipeline.S | 2 +-
tests/tcg/xtensa/test_quo.S | 2 +-
tests/tcg/xtensa/test_rem.S | 2 +-
tests/tcg/xtensa/test_rst0.S | 2 +-
tests/tcg/xtensa/test_s32c1i.S | 2 +-
tests/tcg/xtensa/test_sar.S | 2 +-
tests/tcg/xtensa/test_sext.S | 2 +-
tests/tcg/xtensa/test_shift.S | 2 +-
tests/tcg/xtensa/test_sr.S | 2 +-
tests/tcg/xtensa/test_timer.S | 2 +-
tests/tcg/xtensa/test_windowed.S | 2 +-
30 files changed, 37 insertions(+), 32 deletions(-)
diff --git a/tests/tcg/xtensa/Makefile b/tests/tcg/xtensa/Makefile
index 1b519ca..38f23b1 100644
--- a/tests/tcg/xtensa/Makefile
+++ b/tests/tcg/xtensa/Makefile
@@ -1,10 +1,11 @@
-include ../../../config-host.mak
-CROSS=xtensa-dc232b-elf-
+CORE=dc232b
+CROSS=xtensa-$(CORE)-elf-
ifndef XT
SIM = ../../../xtensa-softmmu/qemu-system-xtensa
-SIMFLAGS = -M sim -cpu dc232b -nographic -semihosting $(EXTFLAGS) -kernel
+SIMFLAGS = -M sim -cpu $(CORE) -nographic -semihosting $(EXTFLAGS) -kernel
SIMDEBUG = -s -S
else
SIM = xt-run
@@ -17,6 +18,8 @@ AS = $(CROSS)gcc -x assembler-with-cpp
LD = $(CROSS)ld
XTENSA_SRC_PATH = $(SRC_PATH)/tests/tcg/xtensa
+INCLUDE_DIRS = $(XTENSA_SRC_PATH) $(SRC_PATH)/target-xtensa/core-$(CORE)
+XTENSA_INC = $(addprefix -I,$(INCLUDE_DIRS))
LDFLAGS = -T$(XTENSA_SRC_PATH)/linker.ld
@@ -56,10 +59,10 @@ TESTCASES += test_windowed.tst
all: build
%.o: $(XTENSA_SRC_PATH)/%.c
- $(CC) -I$(XTENSA_SRC_PATH) $(CFLAGS) -c $< -o $@
+ $(CC) $(XTENSA_INC) $(CFLAGS) -c $< -o $@
%.o: $(XTENSA_SRC_PATH)/%.S
- $(AS) -Wa,-I,$(XTENSA_SRC_PATH) $(ASFLAGS) -c $< -o $@
+ $(CC) $(XTENSA_INC) $(ASFLAGS) -c $< -o $@
%.tst: %.o $(XTENSA_SRC_PATH)/macros.inc $(CRT) Makefile
$(LD) $(LDFLAGS) $(NOSTDFLAGS) $(CRT) $< -o $@
diff --git a/tests/tcg/xtensa/macros.inc b/tests/tcg/xtensa/macros.inc
index ead8528..4ebd30a 100644
--- a/tests/tcg/xtensa/macros.inc
+++ b/tests/tcg/xtensa/macros.inc
@@ -1,3 +1,5 @@
+#include "core-isa.h"
+
.macro test_suite name
.data
status: .word result
diff --git a/tests/tcg/xtensa/test_b.S b/tests/tcg/xtensa/test_b.S
index 6cbe5f1..8e81f95 100644
--- a/tests/tcg/xtensa/test_b.S
+++ b/tests/tcg/xtensa/test_b.S
@@ -1,4 +1,4 @@
-.include "macros.inc"
+#include "macros.inc"
test_suite b
diff --git a/tests/tcg/xtensa/test_bi.S b/tests/tcg/xtensa/test_bi.S
index 6a5f1df..4f94c0c 100644
--- a/tests/tcg/xtensa/test_bi.S
+++ b/tests/tcg/xtensa/test_bi.S
@@ -1,4 +1,4 @@
-.include "macros.inc"
+#include "macros.inc"
test_suite bi
diff --git a/tests/tcg/xtensa/test_boolean.S b/tests/tcg/xtensa/test_boolean.S
index 50e6d2c..eac40e0 100644
--- a/tests/tcg/xtensa/test_boolean.S
+++ b/tests/tcg/xtensa/test_boolean.S
@@ -1,4 +1,4 @@
-.include "macros.inc"
+#include "macros.inc"
test_suite boolean
diff --git a/tests/tcg/xtensa/test_break.S b/tests/tcg/xtensa/test_break.S
index 7574cbe..775cd7c 100644
--- a/tests/tcg/xtensa/test_break.S
+++ b/tests/tcg/xtensa/test_break.S
@@ -1,4 +1,4 @@
-.include "macros.inc"
+#include "macros.inc"
#define debug_level 6
#define debug_vector level6
diff --git a/tests/tcg/xtensa/test_bz.S b/tests/tcg/xtensa/test_bz.S
index f9ba6e2..b681350 100644
--- a/tests/tcg/xtensa/test_bz.S
+++ b/tests/tcg/xtensa/test_bz.S
@@ -1,4 +1,4 @@
-.include "macros.inc"
+#include "macros.inc"
test_suite bz
diff --git a/tests/tcg/xtensa/test_clamps.S b/tests/tcg/xtensa/test_clamps.S
index c186cc9..3efabfd 100644
--- a/tests/tcg/xtensa/test_clamps.S
+++ b/tests/tcg/xtensa/test_clamps.S
@@ -1,4 +1,4 @@
-.include "macros.inc"
+#include "macros.inc"
test_suite clamps
diff --git a/tests/tcg/xtensa/test_extui.S b/tests/tcg/xtensa/test_extui.S
index 5d55451..c32bb82 100644
--- a/tests/tcg/xtensa/test_extui.S
+++ b/tests/tcg/xtensa/test_extui.S
@@ -1,4 +1,4 @@
-.include "macros.inc"
+#include "macros.inc"
test_suite extui
diff --git a/tests/tcg/xtensa/test_fail.S b/tests/tcg/xtensa/test_fail.S
index e8d1b42..1c26d50 100644
--- a/tests/tcg/xtensa/test_fail.S
+++ b/tests/tcg/xtensa/test_fail.S
@@ -1,4 +1,4 @@
-.include "macros.inc"
+#include "macros.inc"
test_suite fail
diff --git a/tests/tcg/xtensa/test_interrupt.S b/tests/tcg/xtensa/test_interrupt.S
index 68b3ee1..334ddab 100644
--- a/tests/tcg/xtensa/test_interrupt.S
+++ b/tests/tcg/xtensa/test_interrupt.S
@@ -1,4 +1,4 @@
-.include "macros.inc"
+#include "macros.inc"
test_suite interrupt
diff --git a/tests/tcg/xtensa/test_loop.S b/tests/tcg/xtensa/test_loop.S
index 1c240e8..5755578 100644
--- a/tests/tcg/xtensa/test_loop.S
+++ b/tests/tcg/xtensa/test_loop.S
@@ -1,4 +1,4 @@
-.include "macros.inc"
+#include "macros.inc"
test_suite loop
diff --git a/tests/tcg/xtensa/test_mac16.S b/tests/tcg/xtensa/test_mac16.S
index 5ddd160..512025d 100644
--- a/tests/tcg/xtensa/test_mac16.S
+++ b/tests/tcg/xtensa/test_mac16.S
@@ -1,4 +1,4 @@
-.include "macros.inc"
+#include "macros.inc"
test_suite mac16
diff --git a/tests/tcg/xtensa/test_max.S b/tests/tcg/xtensa/test_max.S
index 2534c9d..3caa207 100644
--- a/tests/tcg/xtensa/test_max.S
+++ b/tests/tcg/xtensa/test_max.S
@@ -1,4 +1,4 @@
-.include "macros.inc"
+#include "macros.inc"
test_suite max
diff --git a/tests/tcg/xtensa/test_min.S b/tests/tcg/xtensa/test_min.S
index 6d9ddeb..551cf59 100644
--- a/tests/tcg/xtensa/test_min.S
+++ b/tests/tcg/xtensa/test_min.S
@@ -1,4 +1,4 @@
-.include "macros.inc"
+#include "macros.inc"
test_suite min
diff --git a/tests/tcg/xtensa/test_mmu.S b/tests/tcg/xtensa/test_mmu.S
index 4bc34e5..099031f 100644
--- a/tests/tcg/xtensa/test_mmu.S
+++ b/tests/tcg/xtensa/test_mmu.S
@@ -1,4 +1,4 @@
-.include "macros.inc"
+#include "macros.inc"
test_suite mmu
diff --git a/tests/tcg/xtensa/test_mul16.S b/tests/tcg/xtensa/test_mul16.S
index bf94376..98fa704 100644
--- a/tests/tcg/xtensa/test_mul16.S
+++ b/tests/tcg/xtensa/test_mul16.S
@@ -1,4 +1,4 @@
-.include "macros.inc"
+#include "macros.inc"
test_suite mul16
diff --git a/tests/tcg/xtensa/test_mul32.S b/tests/tcg/xtensa/test_mul32.S
index fdaf573..b288ead 100644
--- a/tests/tcg/xtensa/test_mul32.S
+++ b/tests/tcg/xtensa/test_mul32.S
@@ -1,4 +1,4 @@
-.include "macros.inc"
+#include "macros.inc"
test_suite mul32
diff --git a/tests/tcg/xtensa/test_nsa.S b/tests/tcg/xtensa/test_nsa.S
index a5fe5de..479b2e2 100644
--- a/tests/tcg/xtensa/test_nsa.S
+++ b/tests/tcg/xtensa/test_nsa.S
@@ -1,4 +1,4 @@
-.include "macros.inc"
+#include "macros.inc"
test_suite nsa
diff --git a/tests/tcg/xtensa/test_pipeline.S b/tests/tcg/xtensa/test_pipeline.S
index 6be6085..f418c11 100644
--- a/tests/tcg/xtensa/test_pipeline.S
+++ b/tests/tcg/xtensa/test_pipeline.S
@@ -1,4 +1,4 @@
-.include "macros.inc"
+#include "macros.inc"
.purgem test
.macro test name
diff --git a/tests/tcg/xtensa/test_quo.S b/tests/tcg/xtensa/test_quo.S
index 12debf1..5b3ae38 100644
--- a/tests/tcg/xtensa/test_quo.S
+++ b/tests/tcg/xtensa/test_quo.S
@@ -1,4 +1,4 @@
-.include "macros.inc"
+#include "macros.inc"
test_suite quo
diff --git a/tests/tcg/xtensa/test_rem.S b/tests/tcg/xtensa/test_rem.S
index bb0d5fe..6357e52 100644
--- a/tests/tcg/xtensa/test_rem.S
+++ b/tests/tcg/xtensa/test_rem.S
@@ -1,4 +1,4 @@
-.include "macros.inc"
+#include "macros.inc"
test_suite rem
diff --git a/tests/tcg/xtensa/test_rst0.S b/tests/tcg/xtensa/test_rst0.S
index 3eda565..a73366b 100644
--- a/tests/tcg/xtensa/test_rst0.S
+++ b/tests/tcg/xtensa/test_rst0.S
@@ -1,4 +1,4 @@
-.include "macros.inc"
+#include "macros.inc"
test_suite rst0
diff --git a/tests/tcg/xtensa/test_s32c1i.S b/tests/tcg/xtensa/test_s32c1i.S
index 4536015..93b575d 100644
--- a/tests/tcg/xtensa/test_s32c1i.S
+++ b/tests/tcg/xtensa/test_s32c1i.S
@@ -1,4 +1,4 @@
-.include "macros.inc"
+#include "macros.inc"
test_suite s32c1i
diff --git a/tests/tcg/xtensa/test_sar.S b/tests/tcg/xtensa/test_sar.S
index 40c649f..b615a55 100644
--- a/tests/tcg/xtensa/test_sar.S
+++ b/tests/tcg/xtensa/test_sar.S
@@ -1,4 +1,4 @@
-.include "macros.inc"
+#include "macros.inc"
test_suite sar
diff --git a/tests/tcg/xtensa/test_sext.S b/tests/tcg/xtensa/test_sext.S
index 04dc650..087a633 100644
--- a/tests/tcg/xtensa/test_sext.S
+++ b/tests/tcg/xtensa/test_sext.S
@@ -1,4 +1,4 @@
-.include "macros.inc"
+#include "macros.inc"
test_suite sext
diff --git a/tests/tcg/xtensa/test_shift.S b/tests/tcg/xtensa/test_shift.S
index a8e4364..5df9ed4 100644
--- a/tests/tcg/xtensa/test_shift.S
+++ b/tests/tcg/xtensa/test_shift.S
@@ -1,4 +1,4 @@
-.include "macros.inc"
+#include "macros.inc"
test_suite shift
diff --git a/tests/tcg/xtensa/test_sr.S b/tests/tcg/xtensa/test_sr.S
index 470c03d..4fac46e 100644
--- a/tests/tcg/xtensa/test_sr.S
+++ b/tests/tcg/xtensa/test_sr.S
@@ -1,4 +1,4 @@
-.include "macros.inc"
+#include "macros.inc"
test_suite sr
diff --git a/tests/tcg/xtensa/test_timer.S b/tests/tcg/xtensa/test_timer.S
index 1041cc6..f8c6f74 100644
--- a/tests/tcg/xtensa/test_timer.S
+++ b/tests/tcg/xtensa/test_timer.S
@@ -1,4 +1,4 @@
-.include "macros.inc"
+#include "macros.inc"
test_suite timer
diff --git a/tests/tcg/xtensa/test_windowed.S b/tests/tcg/xtensa/test_windowed.S
index cb2d39e..3de6d37 100644
--- a/tests/tcg/xtensa/test_windowed.S
+++ b/tests/tcg/xtensa/test_windowed.S
@@ -1,4 +1,4 @@
-.include "macros.inc"
+#include "macros.inc"
test_suite windowed
--
1.8.1.4
^ permalink raw reply related [flat|nested] 7+ messages in thread* [Qemu-devel] [PATCH 6/6] target-xtensa: add basic tests for cache opcodes
2014-02-11 8:43 [Qemu-devel] [PATCH 0/6] target-xtensa: add basic checks to cache opcodes Max Filippov
` (4 preceding siblings ...)
2014-02-11 8:43 ` [Qemu-devel] [PATCH 5/6] target-xtensa: allow using core configuration in tests Max Filippov
@ 2014-02-11 8:43 ` Max Filippov
5 siblings, 0 replies; 7+ messages in thread
From: Max Filippov @ 2014-02-11 8:43 UTC (permalink / raw)
To: qemu-devel; +Cc: Max Filippov
Test that non-locking prefetch operations don't cause exceptions on
missing TLB and that other 'hit' cache operations do.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
tests/tcg/xtensa/Makefile | 1 +
tests/tcg/xtensa/test_cache.S | 97 +++++++++++++++++++++++++++++++++++++++++++
2 files changed, 98 insertions(+)
create mode 100644 tests/tcg/xtensa/test_cache.S
diff --git a/tests/tcg/xtensa/Makefile b/tests/tcg/xtensa/Makefile
index 38f23b1..a70c92b 100644
--- a/tests/tcg/xtensa/Makefile
+++ b/tests/tcg/xtensa/Makefile
@@ -30,6 +30,7 @@ TESTCASES += test_bi.tst
#TESTCASES += test_boolean.tst
TESTCASES += test_break.tst
TESTCASES += test_bz.tst
+TESTCASES += test_cache.tst
TESTCASES += test_clamps.tst
TESTCASES += test_extui.tst
TESTCASES += test_fail.tst
diff --git a/tests/tcg/xtensa/test_cache.S b/tests/tcg/xtensa/test_cache.S
new file mode 100644
index 0000000..6b2df97
--- /dev/null
+++ b/tests/tcg/xtensa/test_cache.S
@@ -0,0 +1,97 @@
+#include "macros.inc"
+
+.purgem test_init
+.macro test_init
+ call0 cache_unlock_invalidate
+.endm
+
+test_suite cache
+
+.macro pf_op op
+ \op a2, 0
+ \op a3, 0
+ \op a4, 0
+.endm
+
+test prefetch
+ movi a2, 0xd0000000 /* cacheable */
+ movi a3, 0xd8000000 /* non-cacheable */
+ movi a4, 0x00001235 /* unmapped */
+
+ pf_op dpfr
+ pf_op dpfro
+ pf_op dpfw
+ pf_op dpfwo
+ pf_op ipf
+
+ dpfl a2, 0
+ ipfl a2, 0
+test_end
+
+.macro cache_fault op, addr, exc_code
+ set_vector kernel, 2f
+
+ movi a4, \addr
+1:
+ \op a4, 0
+ test_fail
+2:
+ rsr a2, epc1
+ movi a3, 1b
+ assert eq, a2, a3
+ rsr a2, excvaddr
+ assert eq, a2, a4
+ rsr a2, exccause
+ movi a3, \exc_code
+ assert eq, a2, a3
+.endm
+
+test dpfl_tlb_miss
+ cache_fault dpfl, 0x00002345, 24
+test_end
+
+test dhwb_tlb_miss
+ cache_fault dhwb, 0x00002345, 24
+test_end
+
+test dhwbi_tlb_miss
+ cache_fault dhwbi, 0x00002345, 24
+test_end
+
+test dhi_tlb_miss
+ cache_fault dhi, 0x00002345, 24
+test_end
+
+test dhu_tlb_miss
+ cache_fault dhu, 0x00002345, 24
+test_end
+
+
+test ipfl_tlb_miss
+ cache_fault ipfl, 0x00002345, 16
+test_end
+
+test ihu_tlb_miss
+ cache_fault ihu, 0x00002345, 16
+test_end
+
+test ihi_tlb_miss
+ cache_fault ihi, 0x00002345, 16
+test_end
+
+test_suite_end
+
+.macro cache_all op1, op2, size, linesize
+ movi a2, 0
+ movi a3, \size
+1:
+ \op1 a2, 0
+ \op2 a2, 0
+ addi a2, a2, \linesize
+ bltu a2, a3, 1b
+.endm
+
+cache_unlock_invalidate:
+ cache_all diu, dii, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE
+ cache_all iiu, iii, XCHAL_ICACHE_SIZE, XCHAL_ICACHE_LINESIZE
+ ret
--
1.8.1.4
^ permalink raw reply related [flat|nested] 7+ messages in thread