From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36394) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WD8xL-0006FL-Jw for qemu-devel@nongnu.org; Tue, 11 Feb 2014 03:44:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WD8xD-0002iK-73 for qemu-devel@nongnu.org; Tue, 11 Feb 2014 03:44:39 -0500 Received: from mail-lb0-x235.google.com ([2a00:1450:4010:c04::235]:58147) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WD8xC-0002hO-VJ for qemu-devel@nongnu.org; Tue, 11 Feb 2014 03:44:31 -0500 Received: by mail-lb0-f181.google.com with SMTP id z11so4589424lbi.40 for ; Tue, 11 Feb 2014 00:44:29 -0800 (PST) From: Max Filippov Date: Tue, 11 Feb 2014 12:43:35 +0400 Message-Id: <1392108215-20794-7-git-send-email-jcmvbkbc@gmail.com> In-Reply-To: <1392108215-20794-1-git-send-email-jcmvbkbc@gmail.com> References: <1392108215-20794-1-git-send-email-jcmvbkbc@gmail.com> Subject: [Qemu-devel] [PATCH 6/6] target-xtensa: add basic tests for cache opcodes List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Max Filippov Test that non-locking prefetch operations don't cause exceptions on missing TLB and that other 'hit' cache operations do. Signed-off-by: Max Filippov --- tests/tcg/xtensa/Makefile | 1 + tests/tcg/xtensa/test_cache.S | 97 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 98 insertions(+) create mode 100644 tests/tcg/xtensa/test_cache.S diff --git a/tests/tcg/xtensa/Makefile b/tests/tcg/xtensa/Makefile index 38f23b1..a70c92b 100644 --- a/tests/tcg/xtensa/Makefile +++ b/tests/tcg/xtensa/Makefile @@ -30,6 +30,7 @@ TESTCASES += test_bi.tst #TESTCASES += test_boolean.tst TESTCASES += test_break.tst TESTCASES += test_bz.tst +TESTCASES += test_cache.tst TESTCASES += test_clamps.tst TESTCASES += test_extui.tst TESTCASES += test_fail.tst diff --git a/tests/tcg/xtensa/test_cache.S b/tests/tcg/xtensa/test_cache.S new file mode 100644 index 0000000..6b2df97 --- /dev/null +++ b/tests/tcg/xtensa/test_cache.S @@ -0,0 +1,97 @@ +#include "macros.inc" + +.purgem test_init +.macro test_init + call0 cache_unlock_invalidate +.endm + +test_suite cache + +.macro pf_op op + \op a2, 0 + \op a3, 0 + \op a4, 0 +.endm + +test prefetch + movi a2, 0xd0000000 /* cacheable */ + movi a3, 0xd8000000 /* non-cacheable */ + movi a4, 0x00001235 /* unmapped */ + + pf_op dpfr + pf_op dpfro + pf_op dpfw + pf_op dpfwo + pf_op ipf + + dpfl a2, 0 + ipfl a2, 0 +test_end + +.macro cache_fault op, addr, exc_code + set_vector kernel, 2f + + movi a4, \addr +1: + \op a4, 0 + test_fail +2: + rsr a2, epc1 + movi a3, 1b + assert eq, a2, a3 + rsr a2, excvaddr + assert eq, a2, a4 + rsr a2, exccause + movi a3, \exc_code + assert eq, a2, a3 +.endm + +test dpfl_tlb_miss + cache_fault dpfl, 0x00002345, 24 +test_end + +test dhwb_tlb_miss + cache_fault dhwb, 0x00002345, 24 +test_end + +test dhwbi_tlb_miss + cache_fault dhwbi, 0x00002345, 24 +test_end + +test dhi_tlb_miss + cache_fault dhi, 0x00002345, 24 +test_end + +test dhu_tlb_miss + cache_fault dhu, 0x00002345, 24 +test_end + + +test ipfl_tlb_miss + cache_fault ipfl, 0x00002345, 16 +test_end + +test ihu_tlb_miss + cache_fault ihu, 0x00002345, 16 +test_end + +test ihi_tlb_miss + cache_fault ihi, 0x00002345, 16 +test_end + +test_suite_end + +.macro cache_all op1, op2, size, linesize + movi a2, 0 + movi a3, \size +1: + \op1 a2, 0 + \op2 a2, 0 + addi a2, a2, \linesize + bltu a2, a3, 1b +.endm + +cache_unlock_invalidate: + cache_all diu, dii, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE + cache_all iiu, iii, XCHAL_ICACHE_SIZE, XCHAL_ICACHE_LINESIZE + ret -- 1.8.1.4