From: Tom Musta <tommusta@gmail.com>
To: qemu-devel@nongnu.org
Cc: Tom Musta <tommusta@gmail.com>, qemu-ppc@nongnu.org
Subject: [Qemu-devel] [PATCH 10/28] target-ppc: Altivec 2.07: Multiply Even/Odd Word Instructions
Date: Wed, 12 Feb 2014 15:23:01 -0600 [thread overview]
Message-ID: <1392240199-2454-11-git-send-email-tommusta@gmail.com> (raw)
In-Reply-To: <1392240199-2454-1-git-send-email-tommusta@gmail.com>
This patch adds the Multilpy Even/Odd Word instructions that are introduced
in Power ISA Version 2.07:
- Vector Multiply Even Unsigned Word (vmuleuw)
- Vector Multiply Even Signed Word (vmulesw)
- Vector Multiply Odd Unsigned Word (vmulouw)
- Vector Multiply Odd Signed Word (vmulosw)
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/helper.h | 4 ++++
target-ppc/int_helper.c | 2 ++
target-ppc/translate.c | 8 ++++++++
3 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 1106e29..ca18447 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -166,12 +166,16 @@ DEF_HELPER_3(vmrghh, void, avr, avr, avr)
DEF_HELPER_3(vmrghw, void, avr, avr, avr)
DEF_HELPER_3(vmulesb, void, avr, avr, avr)
DEF_HELPER_3(vmulesh, void, avr, avr, avr)
+DEF_HELPER_3(vmulesw, void, avr, avr, avr)
DEF_HELPER_3(vmuleub, void, avr, avr, avr)
DEF_HELPER_3(vmuleuh, void, avr, avr, avr)
+DEF_HELPER_3(vmuleuw, void, avr, avr, avr)
DEF_HELPER_3(vmulosb, void, avr, avr, avr)
DEF_HELPER_3(vmulosh, void, avr, avr, avr)
+DEF_HELPER_3(vmulosw, void, avr, avr, avr)
DEF_HELPER_3(vmuloub, void, avr, avr, avr)
DEF_HELPER_3(vmulouh, void, avr, avr, avr)
+DEF_HELPER_3(vmulouw, void, avr, avr, avr)
DEF_HELPER_3(vsrab, void, avr, avr, avr)
DEF_HELPER_3(vsrah, void, avr, avr, avr)
DEF_HELPER_3(vsraw, void, avr, avr, avr)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 20d34e6..09590c7 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -1005,8 +1005,10 @@ void helper_vmsumuhs(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a,
VMUL_DO(mulo##suffix, mul_element, prod_element, cast, 0)
VMUL(sb, s8, s16, int16_t)
VMUL(sh, s16, s32, int32_t)
+VMUL(sw, s32, s64, int64_t)
VMUL(ub, u8, u16, uint16_t)
VMUL(uh, u16, u32, uint32_t)
+VMUL(uw, u32, u64, uint64_t)
#undef VMUL_DO
#undef VMUL
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index bb1c64e..faee4c3 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6961,12 +6961,16 @@ GEN_VXFORM(vmrglh, 6, 5);
GEN_VXFORM(vmrglw, 6, 6);
GEN_VXFORM(vmuloub, 4, 0);
GEN_VXFORM(vmulouh, 4, 1);
+GEN_VXFORM(vmulouw, 4, 2);
GEN_VXFORM(vmulosb, 4, 4);
GEN_VXFORM(vmulosh, 4, 5);
+GEN_VXFORM(vmulosw, 4, 6);
GEN_VXFORM(vmuleub, 4, 8);
GEN_VXFORM(vmuleuh, 4, 9);
+GEN_VXFORM(vmuleuw, 4, 10);
GEN_VXFORM(vmulesb, 4, 12);
GEN_VXFORM(vmulesh, 4, 13);
+GEN_VXFORM(vmulesw, 4, 14);
GEN_VXFORM(vslb, 2, 4);
GEN_VXFORM(vslh, 2, 5);
GEN_VXFORM(vslw, 2, 6);
@@ -10344,12 +10348,16 @@ GEN_VXFORM(vmrglh, 6, 5),
GEN_VXFORM(vmrglw, 6, 6),
GEN_VXFORM(vmuloub, 4, 0),
GEN_VXFORM(vmulouh, 4, 1),
+GEN_VXFORM_207(vmulouw, 4, 2),
GEN_VXFORM(vmulosb, 4, 4),
GEN_VXFORM(vmulosh, 4, 5),
+GEN_VXFORM_207(vmulosw, 4, 6),
GEN_VXFORM(vmuleub, 4, 8),
GEN_VXFORM(vmuleuh, 4, 9),
+GEN_VXFORM_207(vmuleuw, 4, 10),
GEN_VXFORM(vmulesb, 4, 12),
GEN_VXFORM(vmulesh, 4, 13),
+GEN_VXFORM_207(vmulesw, 4, 14),
GEN_VXFORM(vslb, 2, 4),
GEN_VXFORM(vslh, 2, 5),
GEN_VXFORM(vslw, 2, 6),
--
1.7.1
next prev parent reply other threads:[~2014-02-12 21:24 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-02-12 21:22 [Qemu-devel] [PATCH 00/28] target-ppc: Altivec 2.07 Tom Musta
2014-02-12 21:22 ` [Qemu-devel] [PATCH 01/28] target-ppc: Altivec 2.07: Add Instruction Flag Tom Musta
2014-02-12 21:22 ` [Qemu-devel] [PATCH 02/28] target-ppc: Altivec 2.07: Update AVR Structure Tom Musta
2014-02-12 21:22 ` [Qemu-devel] [PATCH 03/28] target-ppc: Altivec 2.07: Add GEN_VXFORM3 Tom Musta
2014-02-12 21:22 ` [Qemu-devel] [PATCH 04/28] target-ppc: Altivec 2.07: Add Support for Dual Altivec Instructions Tom Musta
2014-02-12 21:22 ` [Qemu-devel] [PATCH 05/28] target-ppc: Altivec 2.07: Add Opcode Macro for VX Form Instructions Tom Musta
2014-02-12 21:22 ` [Qemu-devel] [PATCH 06/28] target-ppc: Altivec 2.07: Add Support for R-Form Dual Instructions Tom Musta
2014-02-12 21:22 ` [Qemu-devel] [PATCH 07/28] target-ppc: Altivec 2.07: Vector Logical Instructions Tom Musta
2014-02-12 21:22 ` [Qemu-devel] [PATCH 08/28] target-ppc: Altivec 2.07: Add/Subtract Unsigned Doubleword Modulo Tom Musta
2014-02-12 21:23 ` [Qemu-devel] [PATCH 09/28] target-ppc: Altivec 2.07: Change VMUL_DO to Support 64-bit Integers Tom Musta
2014-02-12 21:23 ` Tom Musta [this message]
2014-02-12 21:23 ` [Qemu-devel] [PATCH 11/28] target-ppc: Altivec 2.07: vmuluw Instruction Tom Musta
2014-02-12 21:23 ` [Qemu-devel] [PATCH 12/28] target-ppc: Altivec 2.07: Add Vector Count Leading Zeroes Tom Musta
2014-02-12 21:23 ` [Qemu-devel] [PATCH 13/28] target-ppc: Altivec 2.07: Vector Population Count Instructions Tom Musta
2014-02-12 21:23 ` [Qemu-devel] [PATCH 14/28] target-ppc: Altivec 2.07: Vector Min/Max Doubleword Instructions Tom Musta
2014-02-12 21:23 ` [Qemu-devel] [PATCH 15/28] target-ppc: Altivec 2.07: Pack " Tom Musta
2014-02-12 21:23 ` [Qemu-devel] [PATCH 16/28] target-ppc: Altivec 2.07: Unpack Signed Word Instructions Tom Musta
2014-02-12 21:23 ` [Qemu-devel] [PATCH 17/28] target-ppc: Altivec 2.07: Vector Merge Instructions Tom Musta
2014-02-12 21:23 ` [Qemu-devel] [PATCH 18/28] target-ppc: Altivec 2.07: Change Bit Masks to Support 64-bit Rotates and Shifts Tom Musta
2014-02-12 21:23 ` [Qemu-devel] [PATCH 19/28] target-ppc: Altivec 2.07: Vector Doubleword Rotate and Shift Instructions Tom Musta
2014-02-12 21:23 ` [Qemu-devel] [PATCH 20/28] target-ppc: Altivec 2.07: Quadword Addition and Subtracation Tom Musta
2014-02-12 21:23 ` [Qemu-devel] [PATCH 21/28] target-ppc: Altivec 2.07: vbpermq Instruction Tom Musta
2014-02-12 21:23 ` [Qemu-devel] [PATCH 22/28] target-ppc: Altivec 2.07: Doubleword Compares Tom Musta
2014-02-12 21:23 ` [Qemu-devel] [PATCH 23/28] target-ppc: Altivec 2.07: Vector Gather Bits by Bytes Tom Musta
2014-02-24 17:16 ` Richard Henderson
2014-02-12 21:23 ` [Qemu-devel] [PATCH 24/28] target-ppc: Altivec 2.07: Vector Polynomial Multiply Sum Tom Musta
2014-02-24 18:11 ` Richard Henderson
2014-02-12 21:23 ` [Qemu-devel] [PATCH 25/28] target-ppc: Altivec 2.07: Binary Coded Decimal Instructions Tom Musta
2014-02-12 21:23 ` [Qemu-devel] [PATCH 26/28] target-ppc: Altivec 2.07: AES Instructions Tom Musta
2014-02-24 17:59 ` Richard Henderson
2014-02-24 18:11 ` Peter Maydell
2014-02-24 18:22 ` Richard Henderson
2014-02-26 19:22 ` Tom Musta
2014-02-26 22:06 ` Tom Musta
2014-02-26 22:26 ` Richard Henderson
2014-02-12 21:23 ` [Qemu-devel] [PATCH 27/28] target-ppc: Altivec 2.07: Vector SHA Sigma Instructions Tom Musta
2014-02-12 21:23 ` [Qemu-devel] [PATCH 28/28] target-ppc: Altivec 2.07: Vector Permute and Exclusive OR Tom Musta
2014-02-18 18:52 ` [Qemu-devel] [PATCH 00/28] target-ppc: Altivec 2.07 Richard W.M. Jones
2014-02-18 23:27 ` Tom Musta
2014-02-20 10:23 ` Richard W.M. Jones
2014-02-20 12:34 ` Richard W.M. Jones
2014-02-20 12:36 ` [Qemu-devel] [Qemu-ppc] " Alexander Graf
2014-02-20 12:47 ` Richard W.M. Jones
2014-02-21 10:55 ` Aneesh Kumar K.V
2014-02-21 11:21 ` Avik Sil
2014-02-21 11:48 ` Alexander Graf
2014-02-21 11:53 ` Peter Maydell
2014-02-21 12:04 ` Alexander Graf
2014-02-21 12:20 ` Peter Maydell
2014-02-26 11:50 ` Nikunj A Dadhania
2014-02-26 11:58 ` Nikunj A Dadhania
2014-02-20 14:44 ` [Qemu-devel] " Thomas Huth
2014-02-20 14:52 ` Richard W.M. Jones
2014-02-24 6:32 ` [Qemu-devel] [Qemu-ppc] " Nikunj A Dadhania
2014-02-20 15:00 ` Alexander Graf
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