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From: Tom Musta <tommusta@gmail.com>
To: qemu-devel@nongnu.org
Cc: Tom Musta <tommusta@gmail.com>, qemu-ppc@nongnu.org
Subject: [Qemu-devel] [PATCH 24/28] target-ppc: Altivec 2.07: Vector Polynomial Multiply Sum
Date: Wed, 12 Feb 2014 15:23:15 -0600	[thread overview]
Message-ID: <1392240199-2454-25-git-send-email-tommusta@gmail.com> (raw)
In-Reply-To: <1392240199-2454-1-git-send-email-tommusta@gmail.com>

This patch adds the Vectory Polynomial Multiply Sum instructions
introduced in Power ISA Version 2.07:

  - Vectory Polynomial Multiply Sum Byte (vpmsumb)
  - Vectory Polynomial Multiply Sum Halfword (vpmsumh)
  - Vectory Polynomial Multiply Sum Word (vpmsumw)
  - Vectory Polynomial Multiply Sum Doubleword (vpmsumd)

Signed-off-by: Tom Musta <tommusta@gmail.com>
---
 target-ppc/helper.h     |    4 +++
 target-ppc/int_helper.c |   70 +++++++++++++++++++++++++++++++++++++++++++++++
 target-ppc/translate.c  |    8 +++++
 3 files changed, 82 insertions(+), 0 deletions(-)

diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index aca712f..ca9eba5 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -311,6 +311,10 @@ DEF_HELPER_2(vpopcntw, void, avr, avr)
 DEF_HELPER_2(vpopcntd, void, avr, avr)
 DEF_HELPER_3(vbpermq, void, avr, avr, avr)
 DEF_HELPER_2(vgbbd, void, avr, avr)
+DEF_HELPER_3(vpmsumb, void, avr, avr, avr)
+DEF_HELPER_3(vpmsumh, void, avr, avr, avr)
+DEF_HELPER_3(vpmsumw, void, avr, avr, avr)
+DEF_HELPER_3(vpmsumd, void, avr, avr, avr)
 
 DEF_HELPER_2(xsadddp, void, env, i32)
 DEF_HELPER_2(xssubdp, void, env, i32)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index cd0b88a..4e8e507 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -1351,6 +1351,76 @@ void helper_vgbbd(ppc_avr_t *r, ppc_avr_t *b)
     r->u64[1] = t[1];
 }
 
+#define PMSUM(name, srcfld, trgfld, trgtyp)                   \
+void helper_##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)  \
+{                                                             \
+    int i, j;                                                 \
+    trgtyp prod[sizeof(ppc_avr_t)/sizeof(a->srcfld[0])];      \
+                                                              \
+    VECTOR_FOR_INORDER_I(i, srcfld) {                         \
+        prod[i] = 0;                                          \
+        for (j = 0; j < sizeof(a->srcfld[0]) * 8; j++) {      \
+            if (a->srcfld[i] & (1ull<<j)) {                   \
+                prod[i] ^= ((trgtyp)b->srcfld[i] << j);       \
+            }                                                 \
+        }                                                     \
+    }                                                         \
+                                                              \
+    VECTOR_FOR_INORDER_I(i, trgfld) {                         \
+        r->trgfld[i] = prod[2*i] ^ prod[2*i+1];               \
+    }                                                         \
+}
+
+PMSUM(vpmsumb, u8, u16, uint16_t)
+PMSUM(vpmsumh, u16, u32, uint32_t)
+PMSUM(vpmsumw, u32, u64, uint64_t)
+
+void helper_vpmsumd(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+{
+
+#ifdef CONFIG_INT128
+    int i, j;
+    __uint128_t prod[2];
+
+    VECTOR_FOR_INORDER_I(i, u64) {
+        prod[i] = 0;
+        for (j = 0; j < 64; j++) {
+            if (a->u64[i] & (1ull<<j)) {
+                prod[i] ^= (((__uint128_t)b->u64[i]) << j);
+            }
+        }
+    }
+
+    r->u128 = prod[0] ^ prod[1];
+
+#else
+    int i, j;
+    ppc_avr_t prod[2];
+
+    VECTOR_FOR_INORDER_I(i, u64) {
+        prod[i].u64[LO_IDX] = prod[i].u64[HI_IDX] = 0;
+        for (j = 0; j < 64; j++) {
+            if (a->u64[i] & (1ull<<j)) {
+                ppc_avr_t bshift;
+                if (j == 0) {
+                    bshift.u64[HI_IDX] = 0;
+                    bshift.u64[LO_IDX] = b->u64[i];
+                } else {
+                    bshift.u64[HI_IDX] = b->u64[i] >> (64-j);
+                    bshift.u64[LO_IDX] = b->u64[i] << j;
+                }
+                prod[i].u64[LO_IDX] ^= bshift.u64[LO_IDX];
+                prod[i].u64[HI_IDX] ^= bshift.u64[HI_IDX];
+            }
+        }
+    }
+
+    r->u64[LO_IDX] = prod[0].u64[LO_IDX] ^ prod[1].u64[LO_IDX];
+    r->u64[HI_IDX] = prod[0].u64[HI_IDX] ^ prod[1].u64[HI_IDX];
+#endif
+}
+
+
 #if defined(HOST_WORDS_BIGENDIAN)
 #define PKBIG 1
 #else
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 86cdfbe..c53a4ad 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7370,6 +7370,10 @@ GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
                 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
 GEN_VXFORM(vbpermq, 6, 21);
 GEN_VXFORM_NOA(vgbbd, 6, 20);
+GEN_VXFORM(vpmsumb, 4, 16)
+GEN_VXFORM(vpmsumh, 4, 17)
+GEN_VXFORM(vpmsumw, 4, 18)
+GEN_VXFORM(vpmsumd, 4, 19)
 
 /***                           VSX extension                               ***/
 
@@ -10596,6 +10600,10 @@ GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
 
 GEN_VXFORM_207(vbpermq, 6, 21),
 GEN_VXFORM_207(vgbbd, 6, 20),
+GEN_VXFORM_207(vpmsumb, 4, 16),
+GEN_VXFORM_207(vpmsumh, 4, 17),
+GEN_VXFORM_207(vpmsumw, 4, 18),
+GEN_VXFORM_207(vpmsumd, 4, 19),
 
 GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
 GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
-- 
1.7.1

  parent reply	other threads:[~2014-02-12 21:24 UTC|newest]

Thread overview: 55+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-02-12 21:22 [Qemu-devel] [PATCH 00/28] target-ppc: Altivec 2.07 Tom Musta
2014-02-12 21:22 ` [Qemu-devel] [PATCH 01/28] target-ppc: Altivec 2.07: Add Instruction Flag Tom Musta
2014-02-12 21:22 ` [Qemu-devel] [PATCH 02/28] target-ppc: Altivec 2.07: Update AVR Structure Tom Musta
2014-02-12 21:22 ` [Qemu-devel] [PATCH 03/28] target-ppc: Altivec 2.07: Add GEN_VXFORM3 Tom Musta
2014-02-12 21:22 ` [Qemu-devel] [PATCH 04/28] target-ppc: Altivec 2.07: Add Support for Dual Altivec Instructions Tom Musta
2014-02-12 21:22 ` [Qemu-devel] [PATCH 05/28] target-ppc: Altivec 2.07: Add Opcode Macro for VX Form Instructions Tom Musta
2014-02-12 21:22 ` [Qemu-devel] [PATCH 06/28] target-ppc: Altivec 2.07: Add Support for R-Form Dual Instructions Tom Musta
2014-02-12 21:22 ` [Qemu-devel] [PATCH 07/28] target-ppc: Altivec 2.07: Vector Logical Instructions Tom Musta
2014-02-12 21:22 ` [Qemu-devel] [PATCH 08/28] target-ppc: Altivec 2.07: Add/Subtract Unsigned Doubleword Modulo Tom Musta
2014-02-12 21:23 ` [Qemu-devel] [PATCH 09/28] target-ppc: Altivec 2.07: Change VMUL_DO to Support 64-bit Integers Tom Musta
2014-02-12 21:23 ` [Qemu-devel] [PATCH 10/28] target-ppc: Altivec 2.07: Multiply Even/Odd Word Instructions Tom Musta
2014-02-12 21:23 ` [Qemu-devel] [PATCH 11/28] target-ppc: Altivec 2.07: vmuluw Instruction Tom Musta
2014-02-12 21:23 ` [Qemu-devel] [PATCH 12/28] target-ppc: Altivec 2.07: Add Vector Count Leading Zeroes Tom Musta
2014-02-12 21:23 ` [Qemu-devel] [PATCH 13/28] target-ppc: Altivec 2.07: Vector Population Count Instructions Tom Musta
2014-02-12 21:23 ` [Qemu-devel] [PATCH 14/28] target-ppc: Altivec 2.07: Vector Min/Max Doubleword Instructions Tom Musta
2014-02-12 21:23 ` [Qemu-devel] [PATCH 15/28] target-ppc: Altivec 2.07: Pack " Tom Musta
2014-02-12 21:23 ` [Qemu-devel] [PATCH 16/28] target-ppc: Altivec 2.07: Unpack Signed Word Instructions Tom Musta
2014-02-12 21:23 ` [Qemu-devel] [PATCH 17/28] target-ppc: Altivec 2.07: Vector Merge Instructions Tom Musta
2014-02-12 21:23 ` [Qemu-devel] [PATCH 18/28] target-ppc: Altivec 2.07: Change Bit Masks to Support 64-bit Rotates and Shifts Tom Musta
2014-02-12 21:23 ` [Qemu-devel] [PATCH 19/28] target-ppc: Altivec 2.07: Vector Doubleword Rotate and Shift Instructions Tom Musta
2014-02-12 21:23 ` [Qemu-devel] [PATCH 20/28] target-ppc: Altivec 2.07: Quadword Addition and Subtracation Tom Musta
2014-02-12 21:23 ` [Qemu-devel] [PATCH 21/28] target-ppc: Altivec 2.07: vbpermq Instruction Tom Musta
2014-02-12 21:23 ` [Qemu-devel] [PATCH 22/28] target-ppc: Altivec 2.07: Doubleword Compares Tom Musta
2014-02-12 21:23 ` [Qemu-devel] [PATCH 23/28] target-ppc: Altivec 2.07: Vector Gather Bits by Bytes Tom Musta
2014-02-24 17:16   ` Richard Henderson
2014-02-12 21:23 ` Tom Musta [this message]
2014-02-24 18:11   ` [Qemu-devel] [PATCH 24/28] target-ppc: Altivec 2.07: Vector Polynomial Multiply Sum Richard Henderson
2014-02-12 21:23 ` [Qemu-devel] [PATCH 25/28] target-ppc: Altivec 2.07: Binary Coded Decimal Instructions Tom Musta
2014-02-12 21:23 ` [Qemu-devel] [PATCH 26/28] target-ppc: Altivec 2.07: AES Instructions Tom Musta
2014-02-24 17:59   ` Richard Henderson
2014-02-24 18:11     ` Peter Maydell
2014-02-24 18:22       ` Richard Henderson
2014-02-26 19:22     ` Tom Musta
2014-02-26 22:06       ` Tom Musta
2014-02-26 22:26         ` Richard Henderson
2014-02-12 21:23 ` [Qemu-devel] [PATCH 27/28] target-ppc: Altivec 2.07: Vector SHA Sigma Instructions Tom Musta
2014-02-12 21:23 ` [Qemu-devel] [PATCH 28/28] target-ppc: Altivec 2.07: Vector Permute and Exclusive OR Tom Musta
2014-02-18 18:52 ` [Qemu-devel] [PATCH 00/28] target-ppc: Altivec 2.07 Richard W.M. Jones
2014-02-18 23:27   ` Tom Musta
2014-02-20 10:23     ` Richard W.M. Jones
2014-02-20 12:34       ` Richard W.M. Jones
2014-02-20 12:36         ` [Qemu-devel] [Qemu-ppc] " Alexander Graf
2014-02-20 12:47           ` Richard W.M. Jones
2014-02-21 10:55           ` Aneesh Kumar K.V
2014-02-21 11:21             ` Avik Sil
2014-02-21 11:48               ` Alexander Graf
2014-02-21 11:53                 ` Peter Maydell
2014-02-21 12:04                   ` Alexander Graf
2014-02-21 12:20                     ` Peter Maydell
2014-02-26 11:50                       ` Nikunj A Dadhania
2014-02-26 11:58                         ` Nikunj A Dadhania
2014-02-20 14:44         ` [Qemu-devel] " Thomas Huth
2014-02-20 14:52           ` Richard W.M. Jones
2014-02-24  6:32             ` [Qemu-devel] [Qemu-ppc] " Nikunj A Dadhania
2014-02-20 15:00 ` Alexander Graf

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