From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37230) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WDhHg-00005c-00 for qemu-devel@nongnu.org; Wed, 12 Feb 2014 16:24:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WDhHX-0002ue-Ai for qemu-devel@nongnu.org; Wed, 12 Feb 2014 16:23:55 -0500 From: Tom Musta Date: Wed, 12 Feb 2014 15:22:55 -0600 Message-Id: <1392240199-2454-5-git-send-email-tommusta@gmail.com> In-Reply-To: <1392240199-2454-1-git-send-email-tommusta@gmail.com> References: <1392240199-2454-1-git-send-email-tommusta@gmail.com> Subject: [Qemu-devel] [PATCH 04/28] target-ppc: Altivec 2.07: Add Support for Dual Altivec Instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Tom Musta , qemu-ppc@nongnu.org Some Alitvec instructions introduced in Power ISA Version 2.07 use bit 31 (aka the "Rc" bit) as an opcode bit. However, QEMU for PowerPC uses bits 0-5 and 21-30 for opcodes and not bit 31. This patch introduces macros that will handle this situation by injecting an auxiliary handler which decodes bit 31 in invokes one of two standard handlers. Since the instructions are not, in general, from the same version of the ISA, two sets of PPC_*/PPC2_* instruction tags are supported. Signed-off-by: Tom Musta --- target-ppc/translate.c | 24 ++++++++++++++++++++++++ 1 files changed, 24 insertions(+), 0 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 6ba0171..2ad7348 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -6902,6 +6902,26 @@ static void glue(gen_, name)(DisasContext *ctx) \ tcg_temp_free_ptr(rd); \ } +/* + * Support for Altivec instruction pairs that use bit 31 (Rc) as + * an opcode bit. In general, these pairs come from different + * versions of the ISA, so we must also support a pair of flags for + * each instruction. + */ +#define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \ +static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ +{ \ + if ((Rc(ctx->opcode) == 0) && \ + ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \ + gen_##name0(ctx); \ + } else if ((Rc(ctx->opcode) == 1) && \ + ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \ + gen_##name1(ctx); \ + } else { \ + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ + } \ +} + GEN_VXFORM(vaddubm, 0, 0); GEN_VXFORM(vadduhm, 0, 1); GEN_VXFORM(vadduwm, 0, 2); @@ -10233,6 +10253,10 @@ GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20), #undef GEN_VXFORM #define GEN_VXFORM(name, opc2, opc3) \ GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) +#undef GEN_VXFORM_DUAL +#define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \ +GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1) + GEN_VXFORM(vaddubm, 0, 0), GEN_VXFORM(vadduhm, 0, 1), GEN_VXFORM(vadduwm, 0, 2), -- 1.7.1