[Qemu-devel] [PATCH v3 00/31] A64 system emulation prequisites

[Peter Maydell <peter.maydell@linaro.org>]

Here's the latest patchset aimed towards implementing AArch64
system emulation.

Patch 1 is an actually working version of a fix for a problem
I tried to deal with incorrectly in the previous series.
Following patches are implementations of AArch64 views of various
system registers -- these generally got review last time around but
I resend them as they depend on patch 1.
Then we start to get into new stuff:
 * implementation of WFI (very simple)
 * moving the exception-mask DAIF bits out of pstate and uncached_cpsr
   so they're in env->daif in all situations. This allows us to have
   simple code in places like cpu-exec.c that doesn't need to consider
   what kind of core it's running on. I thought about keeping these
   in pstate but that seemed a bit odd for 32 bit cores and the ARM ARM
   seems to want to encourage thinking about all these bits of PSTATE as
   being genuinely separate.
 * handling of exception syndrome information: generally we have to
   update everywhere where we generate an exception to make sure we
   record the details to be presented to EL1 in the syndrome register.
   In this patchset we provide all the infrastructure and fix basically
   everything except data and insn abort exceptions. (The code that
   actually reads env->exception.syndrome will be the AArch64 exception
   entry code, which isn't in this patchset.)
 * adding FP-enabled checks (including fixing the VFP-enable checks
   for A32/T32 code to check the CPACR which an AArch64 EL1 will be
   using as well as the FPSCR.EN which AArch32 Linux kernels use). I
   apologise for the "add checks" part of the patchset being pretty
   near unreviewable; I have done an exhaustive test to confirm there
   are checks on every code path that needs them, though. I had thought
   we could simply put the check at the top level of the decoder, but
   this gives wrong syndrome information for undefined instructions
   in the FP-related areas of the instruction space.
 * update of the page-table-walk code to support 64-bit VAs

This still isn't enough to actually boot an AArch64 kernel, but it's
getting pretty close (remaining parts missing are a DC ZVA implementation,
a definition of a Cortex-A57, and exception entry/exit code, and we
have working code for all of those).

If anything in here doesn't seem to make enough sense without
the remaining code, just let me know and I'll hold onto it.
I think the "add AArch64 version of $foo register" patches will
be good to go into target-arm.next assuming I haven't messed up
patch 1 again, and then the rest of the patchset will be a rather
more maintainable size.

thanks
-- PMM

Peter Maydell (30):
  target-arm: Fix raw read and write functions on AArch64 registers
  target-arm: A64: Make cache ID registers visible to AArch64
  target-arm: Implement AArch64 CurrentEL sysreg
  target-arm: Implement AArch64 MIDR_EL1
  target-arm: Implement AArch64 cache invalidate/clean ops
  target-arm: Implement AArch64 TLB invalidate ops
  target-arm: Implement AArch64 dummy MDSCR_EL1
  target-arm: Implement AArch64 memory attribute registers
  target-arm: Implement AArch64 SCTLR_EL1
  target-arm: Implement AArch64 TCR_EL1
  target-arm: Implement AArch64 VBAR_EL1
  target-arm: Implement AArch64 TTBR*
  target-arm: Implement AArch64 MPIDR
  target-arm: Implement AArch64 generic timers
  target-arm: Implement AArch64 ID and feature registers
  target-arm: Implement AArch64 dummy breakpoint and watchpoint
    registers
  target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI
  target-arm: Get MMU index information correct for A64 code
  target-arm: A64: Implement WFI
  target-arm: Store AIF bits in env->pstate for AArch32
  target-arm: Implement AArch64 DAIF system register
  target-arm: A64: Implement MSR (immediate) instructions
  target-arm: Implement AArch64 view of CPACR
  target-arm: Add utility function for checking AA32/64 state of an EL
  target-arm: Define exception record for AArch64 exceptions
  target-arm: Provide correct syndrome information for cpreg access
    traps
  target-arm: Add support for generating exceptions with syndrome
    information
  target-arm: A64: Correctly fault FP/Neon if CPACR.FPEN set
  target-arm: A64: Add assertion that FP access was checked
  target-arm: Fix VFP enables for AArch32 EL0 under AArch64 EL1

Rob Herring (1):
  target-arm: Add v8 mmu translation support

 cpu-exec.c                 |   4 +-
 hw/arm/pxa2xx.c            |   6 +-
 linux-user/main.c          |  56 ++--
 target-arm/cpu-qom.h       |  10 +
 target-arm/cpu.c           |  19 +-
 target-arm/cpu.h           | 262 ++++++++++++++++--
 target-arm/cpu64.c         |   1 +
 target-arm/helper.c        | 649 +++++++++++++++++++++++++++++++++++----------
 target-arm/helper.h        |   7 +-
 target-arm/machine.c       |   3 +
 target-arm/op_helper.c     |  52 +++-
 target-arm/translate-a64.c | 404 ++++++++++++++++++++++++----
 target-arm/translate.c     | 167 +++++++++---
 target-arm/translate.h     |  15 +-
 14 files changed, 1358 insertions(+), 297 deletions(-)

-- 
1.8.5