From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52502) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WEhmG-0002zu-V5 for qemu-devel@nongnu.org; Sat, 15 Feb 2014 11:07:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WEhmG-0003T0-2X for qemu-devel@nongnu.org; Sat, 15 Feb 2014 11:07:40 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:45775) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WEhmF-0003OX-S3 for qemu-devel@nongnu.org; Sat, 15 Feb 2014 11:07:40 -0500 From: Peter Maydell Date: Sat, 15 Feb 2014 16:07:02 +0000 Message-Id: <1392480444-25565-10-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1392480444-25565-1-git-send-email-peter.maydell@linaro.org> References: <1392480444-25565-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH v3 09/31] target-arm: Implement AArch64 SCTLR_EL1 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Rob Herring , Peter Crosthwaite , patches@linaro.org, Michael Matz , Alexander Graf , Claudio Fontana , Dirk Mueller , Will Newton , Laurent Desnogues , =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvmarm@lists.cs.columbia.edu, Christoffer Dall , Richard Henderson Implement the AArch64 view of the system control register SCTLR_EL1. Signed-off-by: Peter Maydell Reviewed-by: Peter Crosthwaite --- target-arm/cpu.h | 2 +- target-arm/helper.c | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 51fa634..74b1122 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -169,7 +169,7 @@ typedef struct CPUARMState { struct { uint32_t c0_cpuid; uint64_t c0_cssel; /* Cache size selection. */ - uint32_t c1_sys; /* System control register. */ + uint64_t c1_sys; /* System control register. */ uint32_t c1_coproc; /* Coprocessor access register. */ uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ uint32_t c1_scr; /* secure config register. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index 0e459f1..0a9036a 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1948,7 +1948,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) /* Generic registers whose values depend on the implementation */ { ARMCPRegInfo sctlr = { - .name = "SCTLR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, + .name = "SCTLR", .state = ARM_CP_STATE_BOTH, + .opc0 = 3, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys), .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr, .raw_writefn = raw_write, -- 1.8.5