From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52491) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WEhmG-0002zV-Ov for qemu-devel@nongnu.org; Sat, 15 Feb 2014 11:07:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WEhmF-0003SY-Et for qemu-devel@nongnu.org; Sat, 15 Feb 2014 11:07:40 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:45775) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WEhmF-0003OX-8G for qemu-devel@nongnu.org; Sat, 15 Feb 2014 11:07:39 -0500 From: Peter Maydell Date: Sat, 15 Feb 2014 16:07:03 +0000 Message-Id: <1392480444-25565-11-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1392480444-25565-1-git-send-email-peter.maydell@linaro.org> References: <1392480444-25565-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH v3 10/31] target-arm: Implement AArch64 TCR_EL1 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Rob Herring , Peter Crosthwaite , patches@linaro.org, Michael Matz , Alexander Graf , Claudio Fontana , Dirk Mueller , Will Newton , Laurent Desnogues , =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvmarm@lists.cs.columbia.edu, Christoffer Dall , Richard Henderson Implement the AArch64 TCR_EL1, which is the 64 bit view of the AArch32 TTBCR. (The uses of the bits in the register are completely different, but in any given situation the CPU will always interpret them one way or the other. In fact for QEMU EL1 is always 64 bit, but we share the state field because this is the correct mapping to permit a future implementation of EL2.) We also make the AArch64 view the 'master' as far as migration and reset is concerned. Signed-off-by: Peter Maydell Reviewed-by: Peter Crosthwaite --- target-arm/cpu.h | 2 +- target-arm/helper.c | 19 ++++++++++++++++--- 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 74b1122..4e87064 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -177,7 +177,7 @@ typedef struct CPUARMState { uint32_t c2_base0_hi; /* MMU translation table base 0, high 32 bits */ uint32_t c2_base1; /* MMU translation table base 0. */ uint32_t c2_base1_hi; /* MMU translation table base 1, high 32 bits */ - uint32_t c2_control; /* MMU translation table base control. */ + uint64_t c2_control; /* MMU translation table base control. */ uint32_t c2_mask; /* MMU translation table base selection mask. */ uint32_t c2_base_mask; /* MMU translation table base 0 mask. */ uint32_t c2_data; /* MPU data cachable bits. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index 0a9036a..95c9cac 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1215,6 +1215,14 @@ static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) env->cp15.c2_mask = 0; } +static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */ + tlb_flush(env, 1); + env->cp15.c2_control = value; +} + static const ARMCPRegInfo vmsa_cp_reginfo[] = { { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL1_RW, @@ -1228,10 +1236,15 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { { .name = "TTBR1", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c2_base1), .resetvalue = 0, }, - { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, - .access = PL1_RW, .writefn = vmsa_ttbcr_write, - .resetfn = vmsa_ttbcr_reset, .raw_writefn = vmsa_ttbcr_raw_write, + { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, + .access = PL1_RW, .writefn = vmsa_tcr_el1_write, + .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write, .fieldoffset = offsetof(CPUARMState, cp15.c2_control) }, + { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, + .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, .writefn = vmsa_ttbcr_write, + .resetfn = arm_cp_reset_ignore, .raw_writefn = vmsa_ttbcr_raw_write, + .fieldoffset = offsetoflow32(CPUARMState, cp15.c2_control) }, { .name = "DFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_data), .resetvalue = 0, }, -- 1.8.5