From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52753) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WEhmS-0003NO-Cp for qemu-devel@nongnu.org; Sat, 15 Feb 2014 11:07:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WEhmO-0003Xp-1Y for qemu-devel@nongnu.org; Sat, 15 Feb 2014 11:07:52 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:45775) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WEhmN-0003OX-Qu for qemu-devel@nongnu.org; Sat, 15 Feb 2014 11:07:47 -0500 From: Peter Maydell Date: Sat, 15 Feb 2014 16:06:57 +0000 Message-Id: <1392480444-25565-5-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1392480444-25565-1-git-send-email-peter.maydell@linaro.org> References: <1392480444-25565-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH v3 04/31] target-arm: Implement AArch64 MIDR_EL1 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Rob Herring , Peter Crosthwaite , patches@linaro.org, Michael Matz , Alexander Graf , Claudio Fontana , Dirk Mueller , Will Newton , Laurent Desnogues , =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvmarm@lists.cs.columbia.edu, Christoffer Dall , Richard Henderson Implement the AArch64 view of the MIDR system register (for AArch64 it is a simple constant, unlike the complicated mess that TI925 imposes on the 32-bit view). Signed-off-by: Peter Maydell Reviewed-by: Peter Crosthwaite --- target-arm/helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 73dcaf6..cad6bbe 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1720,6 +1720,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) .writefn = arm_cp_write_ignore, .raw_writefn = raw_write, .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), .type = ARM_CP_OVERRIDE }, + { .name = "MIDR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .opc2 = 0, .crn = 0, .crm = 0, + .access = PL1_R, .resetvalue = cpu->midr, .type = ARM_CP_CONST }, { .name = "CTR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, -- 1.8.5