From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39281) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WEj5e-0002Hm-6w for qemu-devel@nongnu.org; Sat, 15 Feb 2014 12:31:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WEj5R-0004FN-UH for qemu-devel@nongnu.org; Sat, 15 Feb 2014 12:31:46 -0500 Received: from mail-lb0-x231.google.com ([2a00:1450:4010:c04::231]:61924) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WEj5R-0004FD-El for qemu-devel@nongnu.org; Sat, 15 Feb 2014 12:31:33 -0500 Received: by mail-lb0-f177.google.com with SMTP id 10so8648524lbg.36 for ; Sat, 15 Feb 2014 09:31:32 -0800 (PST) From: Max Filippov Date: Sat, 15 Feb 2014 21:30:57 +0400 Message-Id: <1392485457-3356-3-git-send-email-jcmvbkbc@gmail.com> In-Reply-To: <1392485457-3356-1-git-send-email-jcmvbkbc@gmail.com> References: <1392485457-3356-1-git-send-email-jcmvbkbc@gmail.com> Subject: [Qemu-devel] [PATCH 2/2] target-xtensa: provide HW confg ID registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Max Filippov Signed-off-by: Max Filippov --- target-xtensa/cpu.c | 2 ++ target-xtensa/cpu.h | 4 ++++ target-xtensa/overlay_tool.h | 9 ++++++++- target-xtensa/translate.c | 9 +++++++-- 4 files changed, 21 insertions(+), 3 deletions(-) diff --git a/target-xtensa/cpu.c b/target-xtensa/cpu.c index 66a0c8a..16f01de 100644 --- a/target-xtensa/cpu.c +++ b/target-xtensa/cpu.c @@ -59,6 +59,8 @@ static void xtensa_cpu_reset(CPUState *s) env->sregs[CACHEATTR] = 0x22222222; env->sregs[ATOMCTL] = xtensa_option_enabled(env->config, XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15; + env->sregs[CONFIGID0] = env->config->configid[0]; + env->sregs[CONFIGID1] = env->config->configid[1]; env->pending_irq_level = 0; reset_mmu(env); diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h index afdb340..9c5a55b 100644 --- a/target-xtensa/cpu.h +++ b/target-xtensa/cpu.h @@ -135,9 +135,11 @@ enum { IBREAKA = 128, DBREAKA = 144, DBREAKC = 160, + CONFIGID0 = 176, EPC1 = 177, DEPC = 192, EPS2 = 194, + CONFIGID1 = 208, EXCSAVE1 = 209, CPENABLE = 224, INTSET = 226, @@ -322,6 +324,8 @@ typedef struct XtensaConfig { unsigned nibreak; unsigned ndbreak; + uint32_t configid[2]; + uint32_t clock_freq_khz; xtensa_tlb itlb; diff --git a/target-xtensa/overlay_tool.h b/target-xtensa/overlay_tool.h index 25b7970..5a1353e 100644 --- a/target-xtensa/overlay_tool.h +++ b/target-xtensa/overlay_tool.h @@ -320,6 +320,12 @@ .nibreak = XCHAL_NUM_IBREAK, \ .ndbreak = XCHAL_NUM_DBREAK +#define CONFIG_SECTION \ + .configid = { \ + XCHAL_HW_CONFIGID0, \ + XCHAL_HW_CONFIGID1, \ + } + #define DEFAULT_SECTIONS \ .options = XTENSA_OPTIONS, \ .nareg = XCHAL_NUM_AREGS, \ @@ -327,7 +333,8 @@ EXCEPTIONS_SECTION, \ INTERRUPTS_SECTION, \ TLB_SECTION, \ - DEBUG_SECTION + DEBUG_SECTION, \ + CONFIG_SECTION #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 2 diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 6061968..22c0735 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -98,12 +98,15 @@ typedef struct XtensaReg { #define XTENSA_REG(regname, opt) XTENSA_REG_ACCESS(regname, opt, SR_RWX) -#define XTENSA_REG_BITS(regname, opt) { \ +#define XTENSA_REG_BITS_ACCESS(regname, opt, acc) { \ .name = (regname), \ .opt_bits = (opt), \ - .access = SR_RWX, \ + .access = (acc), \ } +#define XTENSA_REG_BITS(regname, opt) \ + XTENSA_REG_BITS_ACCESS(regname, opt, SR_RWX) + static const XtensaReg sregnames[256] = { [LBEG] = XTENSA_REG("LBEG", XTENSA_OPTION_LOOP), [LEND] = XTENSA_REG("LEND", XTENSA_OPTION_LOOP), @@ -134,6 +137,7 @@ static const XtensaReg sregnames[256] = { [DBREAKA + 1] = XTENSA_REG("DBREAKA1", XTENSA_OPTION_DEBUG), [DBREAKC] = XTENSA_REG("DBREAKC0", XTENSA_OPTION_DEBUG), [DBREAKC + 1] = XTENSA_REG("DBREAKC1", XTENSA_OPTION_DEBUG), + [CONFIGID0] = XTENSA_REG_BITS_ACCESS("CONFIGID0", XTENSA_OPTION_ALL, SR_R), [EPC1] = XTENSA_REG("EPC1", XTENSA_OPTION_EXCEPTION), [EPC1 + 1] = XTENSA_REG("EPC2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), [EPC1 + 2] = XTENSA_REG("EPC3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), @@ -148,6 +152,7 @@ static const XtensaReg sregnames[256] = { [EPS2 + 3] = XTENSA_REG("EPS5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), [EPS2 + 4] = XTENSA_REG("EPS6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), [EPS2 + 5] = XTENSA_REG("EPS7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), + [CONFIGID1] = XTENSA_REG_BITS_ACCESS("CONFIGID1", XTENSA_OPTION_ALL, SR_R), [EXCSAVE1] = XTENSA_REG("EXCSAVE1", XTENSA_OPTION_EXCEPTION), [EXCSAVE1 + 1] = XTENSA_REG("EXCSAVE2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), -- 1.8.1.4