From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34689) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WF6Qh-0006Tr-5v for qemu-devel@nongnu.org; Sun, 16 Feb 2014 13:27:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WF6Qf-0002vX-7I for qemu-devel@nongnu.org; Sun, 16 Feb 2014 13:27:03 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:45950) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WF6Qf-0002vK-0B for qemu-devel@nongnu.org; Sun, 16 Feb 2014 13:27:01 -0500 From: Peter Maydell Date: Sun, 16 Feb 2014 18:21:08 +0000 Message-Id: <1392574872-28725-4-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1392574872-28725-1-git-send-email-peter.maydell@linaro.org> References: <1392574872-28725-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 3/6] target-arm: A64: Implement the wide 3-reg-different operations List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Crosthwaite , patches@linaro.org, Michael Matz , Alexander Graf , Claudio Fontana , Dirk Mueller , Will Newton , Laurent Desnogues , =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvmarm@lists.cs.columbia.edu, Christoffer Dall , Richard Henderson Implement the wide three-reg-different operations: SADDW, UADDW, SSUBW and USUBW. Signed-off-by: Peter Maydell --- target-arm/translate-a64.c | 41 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 809fbdb..511f15e 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -7117,6 +7117,41 @@ static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size, tcg_temp_free_i64(tcg_res[1]); } +static void handle_3rd_wide(DisasContext *s, int is_q, int is_u, int size, + int opcode, int rd, int rn, int rm) +{ + TCGv_i64 tcg_res[2]; + int part = is_q ? 2 : 0; + int pass; + + for (pass = 0; pass < 2; pass++) { + TCGv_i64 tcg_op1 = tcg_temp_new_i64(); + TCGv_i32 tcg_op2 = tcg_temp_new_i32(); + TCGv_i64 tcg_op2_wide = tcg_temp_new_i64(); + static NeonGenWidenFn * const widenfns[3][2] = { + { gen_helper_neon_widen_s8, gen_helper_neon_widen_u8 }, + { gen_helper_neon_widen_s16, gen_helper_neon_widen_u16 }, + { tcg_gen_ext_i32_i64, tcg_gen_extu_i32_i64 }, + }; + NeonGenWidenFn *widenfn = widenfns[size][is_u]; + + read_vec_element(s, tcg_op1, rn, pass, MO_64); + read_vec_element_i32(s, tcg_op2, rm, part + pass, MO_32); + widenfn(tcg_op2_wide, tcg_op2); + tcg_temp_free_i32(tcg_op2); + tcg_res[pass] = tcg_temp_new_i64(); + gen_neon_addl(size, (opcode == 3), + tcg_res[pass], tcg_op1, tcg_op2_wide); + tcg_temp_free_i64(tcg_op1); + tcg_temp_free_i64(tcg_op2_wide); + } + + for (pass = 0; pass < 2; pass++) { + write_vec_element(s, tcg_res[pass], rd, pass, MO_64); + tcg_temp_free_i64(tcg_res[pass]); + } +} + /* C3.6.15 AdvSIMD three different * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 * +---+---+---+-----------+------+---+------+--------+-----+------+------+ @@ -7147,7 +7182,11 @@ static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn) case 1: /* SADDW, SADDW2, UADDW, UADDW2 */ case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */ /* 64 x 128 -> 128 */ - unsupported_encoding(s, insn); + if (size == 3) { + unallocated_encoding(s); + return; + } + handle_3rd_wide(s, is_q, is_u, size, opcode, rd, rn, rm); break; case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */ case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */ -- 1.8.5