From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34669) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WF6Qg-0006Tn-5v for qemu-devel@nongnu.org; Sun, 16 Feb 2014 13:27:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WF6Qe-0002vO-UO for qemu-devel@nongnu.org; Sun, 16 Feb 2014 13:27:02 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:45950) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WF6Qe-0002vK-N7 for qemu-devel@nongnu.org; Sun, 16 Feb 2014 13:27:00 -0500 From: Peter Maydell Date: Sun, 16 Feb 2014 18:21:09 +0000 Message-Id: <1392574872-28725-5-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1392574872-28725-1-git-send-email-peter.maydell@linaro.org> References: <1392574872-28725-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 4/6] target-arm: A64: Implement narrowing three-reg-diff operations List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Crosthwaite , patches@linaro.org, Michael Matz , Alexander Graf , Claudio Fontana , Dirk Mueller , Will Newton , Laurent Desnogues , =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvmarm@lists.cs.columbia.edu, Christoffer Dall , Richard Henderson Implement the narrowing three-reg-diff operations: ADDHN, RADDHN, SUBHN and RSUBHN. Signed-off-by: Peter Maydell --- target-arm/translate-a64.c | 60 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 59 insertions(+), 1 deletion(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 511f15e..cb630d8 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -7152,6 +7152,60 @@ static void handle_3rd_wide(DisasContext *s, int is_q, int is_u, int size, } } +static void do_narrow_high_u32(TCGv_i32 res, TCGv_i64 in) +{ + tcg_gen_shri_i64(in, in, 32); + tcg_gen_trunc_i64_i32(res, in); +} + +static void do_narrow_round_high_u32(TCGv_i32 res, TCGv_i64 in) +{ + tcg_gen_addi_i64(in, in, 1U << 31); + do_narrow_high_u32(res, in); +} + +static void handle_3rd_narrowing(DisasContext *s, int is_q, int is_u, int size, + int opcode, int rd, int rn, int rm) +{ + TCGv_i32 tcg_res[2]; + int part = is_q ? 2 : 0; + int pass; + + for (pass = 0; pass < 2; pass++) { + TCGv_i64 tcg_op1 = tcg_temp_new_i64(); + TCGv_i64 tcg_op2 = tcg_temp_new_i64(); + TCGv_i64 tcg_wideres = tcg_temp_new_i64(); + static NeonGenNarrowFn * const narrowfns[3][2] = { + { gen_helper_neon_narrow_high_u8, + gen_helper_neon_narrow_round_high_u8 }, + { gen_helper_neon_narrow_high_u16, + gen_helper_neon_narrow_round_high_u16 }, + { do_narrow_high_u32, do_narrow_round_high_u32 }, + }; + NeonGenNarrowFn *gennarrow = narrowfns[size][is_u]; + + read_vec_element(s, tcg_op1, rn, pass, MO_64); + read_vec_element(s, tcg_op2, rm, pass, MO_64); + + gen_neon_addl(size, (opcode == 6), tcg_wideres, tcg_op1, tcg_op2); + + tcg_temp_free_i64(tcg_op1); + tcg_temp_free_i64(tcg_op2); + + tcg_res[pass] = tcg_temp_new_i32(); + gennarrow(tcg_res[pass], tcg_wideres); + tcg_temp_free_i64(tcg_wideres); + } + + for (pass = 0; pass < 2; pass++) { + write_vec_element_i32(s, tcg_res[pass], rd, pass + part, MO_32); + tcg_temp_free_i32(tcg_res[pass]); + } + if (!is_q) { + clear_vec_high(s, rd); + } +} + /* C3.6.15 AdvSIMD three different * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 * +---+---+---+-----------+------+---+------+--------+-----+------+------+ @@ -7191,7 +7245,11 @@ static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn) case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */ case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */ /* 128 x 128 -> 64 */ - unsupported_encoding(s, insn); + if (size == 3) { + unallocated_encoding(s); + return; + } + handle_3rd_narrowing(s, is_q, is_u, size, opcode, rd, rn, rm); break; case 14: /* PMULL, PMULL2 */ if (is_u || size == 1 || size == 2) { -- 1.8.5