From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40839) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WFSFb-0004vx-HX for qemu-devel@nongnu.org; Mon, 17 Feb 2014 12:45:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WFSFT-0004dy-0L for qemu-devel@nongnu.org; Mon, 17 Feb 2014 12:45:03 -0500 Received: from mail-ea0-x234.google.com ([2a00:1450:4013:c01::234]:58479) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WFSFS-0004Bf-Ke for qemu-devel@nongnu.org; Mon, 17 Feb 2014 12:44:54 -0500 Received: by mail-ea0-f180.google.com with SMTP id o10so7371216eaj.11 for ; Mon, 17 Feb 2014 09:44:07 -0800 (PST) From: Beniamino Galvani Date: Mon, 17 Feb 2014 18:43:17 +0100 Message-Id: <1392659003-8264-2-git-send-email-b.galvani@gmail.com> In-Reply-To: <1392659003-8264-1-git-send-email-b.galvani@gmail.com> References: <1392659003-8264-1-git-send-email-b.galvani@gmail.com> Subject: [Qemu-devel] [PATCH 1/7] allwinner-a10-pic: set vector address when an interrupt is pending List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Beniamino Galvani , Peter Maydell , Peter Crosthwaite , Li Guang This patch implements proper updating of the vector register which should hold, according to the A10 user manual, the vector address for the interrupt currently active on the CPU IRQ input. Interrupt priority is not implemented at the moment and thus the first pending interrupt is returned. Signed-off-by: Beniamino Galvani --- hw/intc/allwinner-a10-pic.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/hw/intc/allwinner-a10-pic.c b/hw/intc/allwinner-a10-pic.c index 407d563..bb2351f 100644 --- a/hw/intc/allwinner-a10-pic.c +++ b/hw/intc/allwinner-a10-pic.c @@ -23,11 +23,20 @@ static void aw_a10_pic_update(AwA10PICState *s) { uint8_t i; - int irq = 0, fiq = 0; + int irq = 0, fiq = 0, pending; + + s->vector = 0; for (i = 0; i < AW_A10_PIC_REG_NUM; i++) { irq |= s->irq_pending[i] & ~s->mask[i]; fiq |= s->select[i] & s->irq_pending[i] & ~s->mask[i]; + + if (!s->vector) { + pending = ffs(s->irq_pending[i] & ~s->mask[i]); + if (pending) { + s->vector = (i * 32 + pending - 1) * 4; + } + } } qemu_set_irq(s->parent_irq, !!irq); -- 1.7.10.4