From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40642) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WFSFF-0004KJ-KR for qemu-devel@nongnu.org; Mon, 17 Feb 2014 12:44:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WFSF7-0004Qn-90 for qemu-devel@nongnu.org; Mon, 17 Feb 2014 12:44:41 -0500 Received: from mail-ee0-x22f.google.com ([2a00:1450:4013:c00::22f]:51844) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WFSEy-0004Cv-FG for qemu-devel@nongnu.org; Mon, 17 Feb 2014 12:44:33 -0500 Received: by mail-ee0-f47.google.com with SMTP id d49so7248551eek.34 for ; Mon, 17 Feb 2014 09:44:10 -0800 (PST) From: Beniamino Galvani Date: Mon, 17 Feb 2014 18:43:18 +0100 Message-Id: <1392659003-8264-3-git-send-email-b.galvani@gmail.com> In-Reply-To: <1392659003-8264-1-git-send-email-b.galvani@gmail.com> References: <1392659003-8264-1-git-send-email-b.galvani@gmail.com> Subject: [Qemu-devel] [PATCH 2/7] allwinner-a10-pic: fix interrupt clear behaviour List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Beniamino Galvani , Peter Maydell , Peter Crosthwaite , Li Guang According to this mail thread [1], writing to pending register seems to have no effect on actual pending status of interrupts. This means that the only way to clear a pending interrupt is to clear the interrupt source. This patch implements such behaviour. [1] http://lkml.org/lkml/2013/7/6/59 Signed-off-by: Beniamino Galvani --- hw/intc/allwinner-a10-pic.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/intc/allwinner-a10-pic.c b/hw/intc/allwinner-a10-pic.c index bb2351f..afd57ef 100644 --- a/hw/intc/allwinner-a10-pic.c +++ b/hw/intc/allwinner-a10-pic.c @@ -49,6 +49,8 @@ static void aw_a10_pic_set_irq(void *opaque, int irq, int level) if (level) { set_bit(irq % 32, (void *)&s->irq_pending[irq / 32]); + } else { + clear_bit(irq % 32, (void *)&s->irq_pending[irq / 32]); } aw_a10_pic_update(s); } @@ -105,10 +107,10 @@ static void aw_a10_pic_write(void *opaque, hwaddr offset, uint64_t value, s->nmi = value; break; case AW_A10_PIC_IRQ_PENDING ... AW_A10_PIC_IRQ_PENDING + 8: - s->irq_pending[index] &= ~value; + /* Nothing to do */ break; case AW_A10_PIC_FIQ_PENDING ... AW_A10_PIC_FIQ_PENDING + 8: - s->fiq_pending[index] &= ~value; + /* Ditto */ break; case AW_A10_PIC_SELECT ... AW_A10_PIC_SELECT + 8: s->select[index] = value; -- 1.7.10.4