From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40791) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WFSFY-0004rG-MA for qemu-devel@nongnu.org; Mon, 17 Feb 2014 12:45:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WFSFQ-0004cz-4k for qemu-devel@nongnu.org; Mon, 17 Feb 2014 12:45:00 -0500 Received: from mail-ee0-x235.google.com ([2a00:1450:4013:c00::235]:41707) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WFSFM-0004Bz-S5 for qemu-devel@nongnu.org; Mon, 17 Feb 2014 12:44:52 -0500 Received: by mail-ee0-f53.google.com with SMTP id t10so7241856eei.40 for ; Mon, 17 Feb 2014 09:44:12 -0800 (PST) From: Beniamino Galvani Date: Mon, 17 Feb 2014 18:43:19 +0100 Message-Id: <1392659003-8264-4-git-send-email-b.galvani@gmail.com> In-Reply-To: <1392659003-8264-1-git-send-email-b.galvani@gmail.com> References: <1392659003-8264-1-git-send-email-b.galvani@gmail.com> Subject: [Qemu-devel] [PATCH 3/7] allwinner-a10-pit: avoid generation of spurious interrupts List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Beniamino Galvani , Peter Maydell , Peter Crosthwaite , Li Guang The model was generating interrupts for all enabled timers after the expiration of one of them. Avoid this by passing to the timer callback function a structure containing the index of the expired timer. Signed-off-by: Beniamino Galvani --- hw/timer/allwinner-a10-pit.c | 30 +++++++++++++++++++----------- 1 file changed, 19 insertions(+), 11 deletions(-) diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index b27fce8..3e1c183 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -19,6 +19,11 @@ #include "sysemu/sysemu.h" #include "hw/timer/allwinner-a10-pit.h" +typedef struct TimerContext { + AwA10PITState *state; + int index; +} TimerContext; + static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size) { AwA10PITState *s = AW_A10_PIT(opaque); @@ -193,18 +198,17 @@ static void a10_pit_reset(DeviceState *dev) static void a10_pit_timer_cb(void *opaque) { - AwA10PITState *s = AW_A10_PIT(opaque); - uint8_t i; + TimerContext *tc = opaque; + AwA10PITState *s = tc->state; + uint8_t i = tc->index; - for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { - if (s->control[i] & AW_A10_PIT_TIMER_EN) { - s->irq_status |= 1 << i; - if (s->control[i] & AW_A10_PIT_TIMER_MODE) { - ptimer_stop(s->timer[i]); - s->control[i] &= ~AW_A10_PIT_TIMER_EN; - } - qemu_irq_pulse(s->irq[i]); + if (s->control[i] & AW_A10_PIT_TIMER_EN) { + s->irq_status |= 1 << i; + if (s->control[i] & AW_A10_PIT_TIMER_MODE) { + ptimer_stop(s->timer[i]); + s->control[i] &= ~AW_A10_PIT_TIMER_EN; } + qemu_irq_pulse(s->irq[i]); } } @@ -213,6 +217,7 @@ static void a10_pit_init(Object *obj) AwA10PITState *s = AW_A10_PIT(obj); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); QEMUBH * bh[AW_A10_PIT_TIMER_NR]; + TimerContext *tc; uint8_t i; for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { @@ -223,7 +228,10 @@ static void a10_pit_init(Object *obj) sysbus_init_mmio(sbd, &s->iomem); for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { - bh[i] = qemu_bh_new(a10_pit_timer_cb, s); + tc = g_malloc(sizeof(TimerContext)); + tc->state = s; + tc->index = i; + bh[i] = qemu_bh_new(a10_pit_timer_cb, tc); s->timer[i] = ptimer_init(bh[i]); ptimer_set_freq(s->timer[i], 240000); } -- 1.7.10.4