From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40769) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WFSFX-0004oG-1j for qemu-devel@nongnu.org; Mon, 17 Feb 2014 12:45:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WFSFO-0004cK-1z for qemu-devel@nongnu.org; Mon, 17 Feb 2014 12:44:58 -0500 Received: from mail-ea0-f170.google.com ([209.85.215.170]:56998) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WFSFN-0004c3-R3 for qemu-devel@nongnu.org; Mon, 17 Feb 2014 12:44:49 -0500 Received: by mail-ea0-f170.google.com with SMTP id g15so5597031eak.1 for ; Mon, 17 Feb 2014 09:44:14 -0800 (PST) From: Beniamino Galvani Date: Mon, 17 Feb 2014 18:43:20 +0100 Message-Id: <1392659003-8264-5-git-send-email-b.galvani@gmail.com> In-Reply-To: <1392659003-8264-1-git-send-email-b.galvani@gmail.com> References: <1392659003-8264-1-git-send-email-b.galvani@gmail.com> Subject: [Qemu-devel] [PATCH 4/7] allwinner-a10-pit: use level triggered interrupts List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Beniamino Galvani , Peter Maydell , Peter Crosthwaite , Li Guang Converts the interrupt generation logic to the use of level triggered interrupts. Signed-off-by: Beniamino Galvani --- hw/timer/allwinner-a10-pit.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index 3e1c183..4723b25 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -24,6 +24,15 @@ typedef struct TimerContext { int index; } TimerContext; +static void a10_pit_update_irq(AwA10PITState *s) +{ + int i; + + for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { + qemu_set_irq(s->irq[i], s->irq_status & s->irq_enable & (1 << i)); + } +} + static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size) { AwA10PITState *s = AW_A10_PIT(opaque); @@ -79,9 +88,11 @@ static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value, switch (offset) { case AW_A10_PIT_TIMER_IRQ_EN: s->irq_enable = value; + a10_pit_update_irq(s); break; case AW_A10_PIT_TIMER_IRQ_ST: s->irq_status &= ~value; + a10_pit_update_irq(s); break; case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END: index = offset & 0xf0; @@ -208,7 +219,7 @@ static void a10_pit_timer_cb(void *opaque) ptimer_stop(s->timer[i]); s->control[i] &= ~AW_A10_PIT_TIMER_EN; } - qemu_irq_pulse(s->irq[i]); + a10_pit_update_irq(s); } } -- 1.7.10.4