From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60477) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WFZIZ-0005Yw-Hb for qemu-devel@nongnu.org; Mon, 17 Feb 2014 20:16:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WFZIT-0007cg-Nv for qemu-devel@nongnu.org; Mon, 17 Feb 2014 20:16:35 -0500 Received: from mail-qa0-x232.google.com ([2607:f8b0:400d:c00::232]:39054) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WFZIT-0007cY-IM for qemu-devel@nongnu.org; Mon, 17 Feb 2014 20:16:29 -0500 Received: by mail-qa0-f50.google.com with SMTP id cm18so22312191qab.23 for ; Mon, 17 Feb 2014 17:16:29 -0800 (PST) Received: from pike.twiddle.home.com ([12.236.175.36]) by mx.google.com with ESMTPSA id w2sm50415225qad.19.2014.02.17.17.16.27 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Feb 2014 17:16:28 -0800 (PST) Sender: Richard Henderson From: Richard Henderson Date: Mon, 17 Feb 2014 19:16:03 -0600 Message-Id: <1392686165-10706-14-git-send-email-rth@twiddle.net> In-Reply-To: <1392686165-10706-1-git-send-email-rth@twiddle.net> References: <1392686165-10706-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PULL 13/15] tcg/i386: Add tcg_out_vex_modrm List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Prepare for emitting BMI insns which require VEX encoding. Reviewed-by: Paolo Bonzini Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c | 41 ++++++++++++++++++++++++++++++++++++++--- 1 file changed, 38 insertions(+), 3 deletions(-) diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c index 7008b0e..00dbc3b 100644 --- a/tcg/i386/tcg-target.c +++ b/tcg/i386/tcg-target.c @@ -402,9 +402,9 @@ static void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x) rex = 0; rex |= (opc & P_REXW) ? 0x8 : 0x0; /* REX.W */ - rex |= (r & 8) >> 1; /* REX.R */ - rex |= (x & 8) >> 2; /* REX.X */ - rex |= (rm & 8) >> 3; /* REX.B */ + rex |= (r & 8) >> 1; /* REX.R */ + rex |= (x & 8) >> 2; /* REX.X */ + rex |= (rm & 8) >> 3; /* REX.B */ /* P_REXB_{R,RM} indicates that the given register is the low byte. For %[abcd]l we need no REX prefix, but for %{si,di,bp,sp}l we do, @@ -453,6 +453,41 @@ static void tcg_out_modrm(TCGContext *s, int opc, int r, int rm) tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); } +static void tcg_out_vex_modrm(TCGContext *s, int opc, int r, int v, int rm) +{ + int tmp; + + if ((opc & (P_REXW | P_EXT | P_EXT38)) || (rm & 8)) { + /* Three byte VEX prefix. */ + tcg_out8(s, 0xc4); + + /* VEX.m-mmmm */ + if (opc & P_EXT38) { + tmp = 2; + } else if (opc & P_EXT) { + tmp = 1; + } else { + tcg_abort(); + } + tmp |= 0x40; /* VEX.X */ + tmp |= (r & 8 ? 0 : 0x80); /* VEX.R */ + tmp |= (rm & 8 ? 0 : 0x20); /* VEX.B */ + tcg_out8(s, tmp); + + tmp = (opc & P_REXW ? 0x80 : 0); /* VEX.W */ + } else { + /* Two byte VEX prefix. */ + tcg_out8(s, 0xc5); + + tmp = (r & 8 ? 0 : 0x80); /* VEX.R */ + } + tmp |= (opc & P_DATA16 ? 1 : 0); /* VEX.pp */ + tmp |= (~v & 15) << 3; /* VEX.vvvv */ + tcg_out8(s, tmp); + tcg_out8(s, opc); + tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); +} + /* Output an opcode with a full "rm + (index<