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From: Peter Maydell <peter.maydell@linaro.org>
To: Anthony Liguori <aliguori@amazon.com>
Cc: Blue Swirl <blauwirbel@gmail.com>,
	qemu-devel@nongnu.org, Aurelien Jarno <aurelien@aurel32.net>
Subject: [Qemu-devel] [PULL 13/30] target-arm: Remove unused ARMCPUState sr substruct
Date: Thu, 20 Feb 2014 11:17:17 +0000	[thread overview]
Message-ID: <1392895054-13232-14-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1392895054-13232-1-git-send-email-peter.maydell@linaro.org>

Remove the 'struct sr' from ARMCPUState -- it isn't actually used and is
a hangover from the original separate system register implementation used
by the SuSE linux-user-mode-only AArch64 target.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---
 target-arm/cpu.h | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 52894fc..ab57f55 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -217,11 +217,6 @@ typedef struct CPUARMState {
         uint32_t c15_power_control; /* power control */
     } cp15;
 
-    /* System registers (AArch64) */
-    struct {
-        uint64_t tpidr_el0;
-    } sr;
-
     struct {
         uint32_t other_sp;
         uint32_t vecbase;
-- 
1.8.5

  parent reply	other threads:[~2014-02-20 11:19 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-02-20 11:17 [Qemu-devel] [PULL 00/30] target-arm queue Peter Maydell
2014-02-20 11:17 ` [Qemu-devel] [PULL 01/30] hw/intc/arm_gic: Fix NVIC assertion failure Peter Maydell
2014-02-20 11:17 ` [Qemu-devel] [PULL 02/30] target-arm: A64: Implement plain vector SIMD indexed element insns Peter Maydell
2014-02-20 11:17 ` [Qemu-devel] [PULL 03/30] target-arm: A64: Implement long vector x indexed insns Peter Maydell
2014-02-20 11:17 ` [Qemu-devel] [PULL 04/30] target-arm: A64: Implement SIMD scalar indexed instructions Peter Maydell
2014-02-20 11:17 ` [Qemu-devel] [PULL 05/30] target-arm: A64: Implement scalar three different instructions Peter Maydell
2014-02-20 11:17 ` [Qemu-devel] [PULL 06/30] target-arm: A64: Implement SIMD FP compare and set insns Peter Maydell
2014-02-20 11:17 ` [Qemu-devel] [PULL 07/30] target-arm: A64: Implement floating point pairwise insns Peter Maydell
2014-02-20 11:17 ` [Qemu-devel] [PULL 08/30] softfloat: Support halving the result of muladd operation Peter Maydell
2014-02-20 11:17 ` [Qemu-devel] [PULL 09/30] target-arm: A64: Implement remaining 3-same instructions Peter Maydell
2014-02-20 11:17 ` [Qemu-devel] [PULL 10/30] target-arm/kvm-consts.h: Define QEMU constants for known KVM CPUs Peter Maydell
2014-02-20 11:17 ` [Qemu-devel] [PULL 11/30] target-arm: Define names for SCTLR bits Peter Maydell
2014-02-20 11:17 ` [Qemu-devel] [PULL 12/30] target-arm: Restrict check_ap() use of S and R bits to v6 and earlier Peter Maydell
2014-02-20 11:17 ` Peter Maydell [this message]
2014-02-20 11:17 ` [Qemu-devel] [PULL 14/30] target-arm: Log bad system register accesses with LOG_UNIMP Peter Maydell
2014-02-20 11:17 ` [Qemu-devel] [PULL 15/30] target-arm: Stop underdecoding ARM946 PRBS registers Peter Maydell
2014-02-20 11:17 ` [Qemu-devel] [PULL 16/30] target-arm: Split cpreg access checks out from read/write functions Peter Maydell
2014-02-20 11:17 ` [Qemu-devel] [PULL 17/30] target-arm: Convert performance monitor reginfo to accessfn Peter Maydell
2014-02-20 11:17 ` [Qemu-devel] [PULL 18/30] target-arm: Convert generic timer " Peter Maydell
2014-02-20 11:17 ` [Qemu-devel] [PULL 19/30] target-arm: Convert miscellaneous reginfo structs " Peter Maydell
2014-02-20 11:17 ` [Qemu-devel] [PULL 20/30] target-arm: Drop success/fail return from cpreg read and write functions Peter Maydell
2014-02-20 11:17 ` [Qemu-devel] [PULL 21/30] target-arm: Remove unnecessary code now read/write fns can't fail Peter Maydell
2014-02-20 11:17 ` [Qemu-devel] [PULL 22/30] target-arm: Remove failure status return from read/write_raw_cp_reg Peter Maydell
2014-02-20 11:17 ` [Qemu-devel] [PULL 23/30] target-arm: Fix incorrect type for value argument to write_raw_cp_reg Peter Maydell
2014-02-20 11:17 ` [Qemu-devel] [PULL 24/30] target-arm: A64: Implement store-exclusive for system mode Peter Maydell
2014-02-20 11:17 ` [Qemu-devel] [PULL 25/30] target-arm: A64: Add opcode comments to disas_simd_three_reg_diff Peter Maydell
2014-02-20 11:17 ` [Qemu-devel] [PULL 26/30] target-arm: A64: Add most remaining three-reg-diff widening ops Peter Maydell
2014-02-20 11:17 ` [Qemu-devel] [PULL 27/30] target-arm: A64: Implement the wide 3-reg-different operations Peter Maydell
2014-02-20 11:17 ` [Qemu-devel] [PULL 28/30] target-arm: A64: Implement narrowing three-reg-diff operations Peter Maydell
2014-02-20 11:17 ` [Qemu-devel] [PULL 29/30] target-arm: A64: Implement unprivileged load/store Peter Maydell
2014-02-20 11:17 ` [Qemu-devel] [PULL 30/30] linux-user: AArch64: Fix exclusive store of the zero register Peter Maydell
2014-02-21 16:01 ` [Qemu-devel] [PULL 00/30] target-arm queue Peter Maydell

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