From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46904) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WGlJt-0005uc-FT for qemu-devel@nongnu.org; Fri, 21 Feb 2014 03:19:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WGlJj-0001kB-3o for qemu-devel@nongnu.org; Fri, 21 Feb 2014 03:18:53 -0500 Received: from e8.ny.us.ibm.com ([32.97.182.138]:51399) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WGlJi-0001jz-Ui for qemu-devel@nongnu.org; Fri, 21 Feb 2014 03:18:43 -0500 Received: from /spool/local by e8.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Fri, 21 Feb 2014 03:18:42 -0500 From: Michael Roth Date: Fri, 21 Feb 2014 02:17:08 -0600 Message-Id: <1392970647-21528-33-git-send-email-mdroth@linux.vnet.ibm.com> In-Reply-To: <1392970647-21528-1-git-send-email-mdroth@linux.vnet.ibm.com> References: <1392970647-21528-1-git-send-email-mdroth@linux.vnet.ibm.com> Subject: [Qemu-devel] [PATCH 32/51] tcg/optimize: fix known-zero bits for right shift ops List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: lersek@redhat.com, qemu-stable@nongnu.org, Petar.Jovanovic@imgtec.com From: Aurelien Jarno 32-bit versions of sar and shr ops should not propagate known-zero bits from the unused 32 high bits. For sar it could even lead to wrong code being generated. Cc: qemu-stable@nongnu.org Reviewed-by: Paolo Bonzini Signed-off-by: Aurelien Jarno Signed-off-by: Richard Henderson (cherry picked from commit e46b225a3137e62c975c49aaae7bb5f9583cc428) Signed-off-by: Michael Roth --- tcg/optimize.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 89e2d6a..c5cdde2 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -726,16 +726,25 @@ static TCGArg *tcg_constant_folding(TCGContext *s, uint16_t *tcg_opc_ptr, mask = temps[args[1]].mask & mask; break; - CASE_OP_32_64(sar): + case INDEX_op_sar_i32: + if (temps[args[2]].state == TCG_TEMP_CONST) { + mask = (int32_t)temps[args[1]].mask >> temps[args[2]].val; + } + break; + case INDEX_op_sar_i64: if (temps[args[2]].state == TCG_TEMP_CONST) { - mask = ((tcg_target_long)temps[args[1]].mask - >> temps[args[2]].val); + mask = (int64_t)temps[args[1]].mask >> temps[args[2]].val; } break; - CASE_OP_32_64(shr): + case INDEX_op_shr_i32: + if (temps[args[2]].state == TCG_TEMP_CONST) { + mask = (uint32_t)temps[args[1]].mask >> temps[args[2]].val; + } + break; + case INDEX_op_shr_i64: if (temps[args[2]].state == TCG_TEMP_CONST) { - mask = temps[args[1]].mask >> temps[args[2]].val; + mask = (uint64_t)temps[args[1]].mask >> temps[args[2]].val; } break; -- 1.7.9.5