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From: Peter Maydell <peter.maydell@linaro.org>
To: Anthony Liguori <aliguori@amazon.com>
Cc: Blue Swirl <blauwirbel@gmail.com>,
	qemu-devel@nongnu.org, Aurelien Jarno <aurelien@aurel32.net>
Subject: [Qemu-devel] [PULL 09/45] linux-headers: Update from v3.14-rc3
Date: Wed, 26 Feb 2014 18:01:59 +0000	[thread overview]
Message-ID: <1393437755-23586-10-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1393437755-23586-1-git-send-email-peter.maydell@linaro.org>

From: Christoffer Dall <christoffer.dall@linaro.org>

Update to tag v3.14-rc3 (6d0abeca3242a88cab8232e4acd7e2bf088f3bc2)

Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Message-id: 1392687720-26806-2-git-send-email-christoffer.dall@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 linux-headers/asm-arm/kvm.h     | 28 ++++++++++++++++++++++++++++
 linux-headers/asm-arm64/kvm.h   | 30 +++++++++++++++++++++++++++++-
 linux-headers/asm-powerpc/kvm.h |  3 +++
 linux-headers/asm-x86/hyperv.h  | 16 +++++++++++++---
 linux-headers/linux/kvm.h       |  1 +
 5 files changed, 74 insertions(+), 4 deletions(-)

diff --git a/linux-headers/asm-arm/kvm.h b/linux-headers/asm-arm/kvm.h
index c498b60..ef0c878 100644
--- a/linux-headers/asm-arm/kvm.h
+++ b/linux-headers/asm-arm/kvm.h
@@ -119,6 +119,26 @@ struct kvm_arch_memory_slot {
 #define KVM_REG_ARM_32_CRN_MASK		0x0000000000007800
 #define KVM_REG_ARM_32_CRN_SHIFT	11
 
+#define ARM_CP15_REG_SHIFT_MASK(x,n) \
+	(((x) << KVM_REG_ARM_ ## n ## _SHIFT) & KVM_REG_ARM_ ## n ## _MASK)
+
+#define __ARM_CP15_REG(op1,crn,crm,op2) \
+	(KVM_REG_ARM | (15 << KVM_REG_ARM_COPROC_SHIFT) | \
+	ARM_CP15_REG_SHIFT_MASK(op1, OPC1) | \
+	ARM_CP15_REG_SHIFT_MASK(crn, 32_CRN) | \
+	ARM_CP15_REG_SHIFT_MASK(crm, CRM) | \
+	ARM_CP15_REG_SHIFT_MASK(op2, 32_OPC2))
+
+#define ARM_CP15_REG32(...) (__ARM_CP15_REG(__VA_ARGS__) | KVM_REG_SIZE_U32)
+
+#define __ARM_CP15_REG64(op1,crm) \
+	(__ARM_CP15_REG(op1, 0, crm, 0) | KVM_REG_SIZE_U64)
+#define ARM_CP15_REG64(...) __ARM_CP15_REG64(__VA_ARGS__)
+
+#define KVM_REG_ARM_TIMER_CTL		ARM_CP15_REG32(0, 14, 3, 1)
+#define KVM_REG_ARM_TIMER_CNT		ARM_CP15_REG64(1, 14) 
+#define KVM_REG_ARM_TIMER_CVAL		ARM_CP15_REG64(3, 14) 
+
 /* Normal registers are mapped as coprocessor 16. */
 #define KVM_REG_ARM_CORE		(0x0010 << KVM_REG_ARM_COPROC_SHIFT)
 #define KVM_REG_ARM_CORE_REG(name)	(offsetof(struct kvm_regs, name) / 4)
@@ -143,6 +163,14 @@ struct kvm_arch_memory_slot {
 #define KVM_REG_ARM_VFP_FPINST		0x1009
 #define KVM_REG_ARM_VFP_FPINST2		0x100A
 
+/* Device Control API: ARM VGIC */
+#define KVM_DEV_ARM_VGIC_GRP_ADDR	0
+#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS	1
+#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS	2
+#define   KVM_DEV_ARM_VGIC_CPUID_SHIFT	32
+#define   KVM_DEV_ARM_VGIC_CPUID_MASK	(0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
+#define   KVM_DEV_ARM_VGIC_OFFSET_SHIFT	0
+#define   KVM_DEV_ARM_VGIC_OFFSET_MASK	(0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
 
 /* KVM_IRQ_LINE irq field index values */
 #define KVM_ARM_IRQ_TYPE_SHIFT		24
diff --git a/linux-headers/asm-arm64/kvm.h b/linux-headers/asm-arm64/kvm.h
index 5031f42..eaf54a3 100644
--- a/linux-headers/asm-arm64/kvm.h
+++ b/linux-headers/asm-arm64/kvm.h
@@ -55,8 +55,9 @@ struct kvm_regs {
 #define KVM_ARM_TARGET_AEM_V8		0
 #define KVM_ARM_TARGET_FOUNDATION_V8	1
 #define KVM_ARM_TARGET_CORTEX_A57	2
+#define KVM_ARM_TARGET_XGENE_POTENZA	3
 
-#define KVM_ARM_NUM_TARGETS		3
+#define KVM_ARM_NUM_TARGETS		4
 
 /* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
 #define KVM_ARM_DEVICE_TYPE_SHIFT	0
@@ -129,6 +130,33 @@ struct kvm_arch_memory_slot {
 #define KVM_REG_ARM64_SYSREG_OP2_MASK	0x0000000000000007
 #define KVM_REG_ARM64_SYSREG_OP2_SHIFT	0
 
+#define ARM64_SYS_REG_SHIFT_MASK(x,n) \
+	(((x) << KVM_REG_ARM64_SYSREG_ ## n ## _SHIFT) & \
+	KVM_REG_ARM64_SYSREG_ ## n ## _MASK)
+
+#define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \
+	(KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | \
+	ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \
+	ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \
+	ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \
+	ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \
+	ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
+
+#define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64)
+
+#define KVM_REG_ARM_TIMER_CTL		ARM64_SYS_REG(3, 3, 14, 3, 1)
+#define KVM_REG_ARM_TIMER_CNT		ARM64_SYS_REG(3, 3, 14, 3, 2)
+#define KVM_REG_ARM_TIMER_CVAL		ARM64_SYS_REG(3, 3, 14, 0, 2)
+
+/* Device Control API: ARM VGIC */
+#define KVM_DEV_ARM_VGIC_GRP_ADDR	0
+#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS	1
+#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS	2
+#define   KVM_DEV_ARM_VGIC_CPUID_SHIFT	32
+#define   KVM_DEV_ARM_VGIC_CPUID_MASK	(0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
+#define   KVM_DEV_ARM_VGIC_OFFSET_SHIFT	0
+#define   KVM_DEV_ARM_VGIC_OFFSET_MASK	(0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
+
 /* KVM_IRQ_LINE irq field index values */
 #define KVM_ARM_IRQ_TYPE_SHIFT		24
 #define KVM_ARM_IRQ_TYPE_MASK		0xff
diff --git a/linux-headers/asm-powerpc/kvm.h b/linux-headers/asm-powerpc/kvm.h
index 6836ec7..a6665be 100644
--- a/linux-headers/asm-powerpc/kvm.h
+++ b/linux-headers/asm-powerpc/kvm.h
@@ -545,6 +545,7 @@ struct kvm_get_htab_header {
 #define KVM_REG_PPC_TCSCR	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb1)
 #define KVM_REG_PPC_PID		(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb2)
 #define KVM_REG_PPC_ACOP	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb3)
+#define KVM_REG_PPC_WORT	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb4)
 
 #define KVM_REG_PPC_VRSAVE	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb4)
 #define KVM_REG_PPC_LPCR	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb5)
@@ -553,6 +554,8 @@ struct kvm_get_htab_header {
 /* Architecture compatibility level */
 #define KVM_REG_PPC_ARCH_COMPAT	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb7)
 
+#define KVM_REG_PPC_DABRX	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb8)
+
 /* Transactional Memory checkpointed state:
  * This is all GPRs, all VSX regs and a subset of SPRs
  */
diff --git a/linux-headers/asm-x86/hyperv.h b/linux-headers/asm-x86/hyperv.h
index 3b400ee..462efe7 100644
--- a/linux-headers/asm-x86/hyperv.h
+++ b/linux-headers/asm-x86/hyperv.h
@@ -28,6 +28,9 @@
 /* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/
 #define HV_X64_MSR_TIME_REF_COUNT_AVAILABLE	(1 << 1)
 
+/* A partition's reference time stamp counter (TSC) page */
+#define HV_X64_MSR_REFERENCE_TSC		0x40000021
+
 /*
  * There is a single feature flag that signifies the presence of the MSR
  * that can be used to retrieve both the local APIC Timer frequency as
@@ -149,9 +152,6 @@
 /* MSR used to read the per-partition time reference counter */
 #define HV_X64_MSR_TIME_REF_COUNT		0x40000020
 
-/* A partition's reference time stamp counter (TSC) page */
-#define HV_X64_MSR_REFERENCE_TSC		0x40000021
-
 /* MSR used to retrieve the TSC frequency */
 #define HV_X64_MSR_TSC_FREQUENCY		0x40000022
 
@@ -201,6 +201,9 @@
 #define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_MASK	\
 		(~((1ull << HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT) - 1))
 
+#define HV_X64_MSR_TSC_REFERENCE_ENABLE		0x00000001
+#define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT	12
+
 #define HV_PROCESSOR_POWER_STATE_C0		0
 #define HV_PROCESSOR_POWER_STATE_C1		1
 #define HV_PROCESSOR_POWER_STATE_C2		2
@@ -213,4 +216,11 @@
 #define HV_STATUS_INVALID_ALIGNMENT		4
 #define HV_STATUS_INSUFFICIENT_BUFFERS		19
 
+typedef struct _HV_REFERENCE_TSC_PAGE {
+	__u32 tsc_sequence;
+	__u32 res1;
+	__u64 tsc_scale;
+	__s64 tsc_offset;
+} HV_REFERENCE_TSC_PAGE, *PHV_REFERENCE_TSC_PAGE;
+
 #endif
diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index 999fb13..77ad35c 100644
--- a/linux-headers/linux/kvm.h
+++ b/linux-headers/linux/kvm.h
@@ -854,6 +854,7 @@ struct kvm_device_attr {
 #define  KVM_DEV_VFIO_GROUP			1
 #define   KVM_DEV_VFIO_GROUP_ADD			1
 #define   KVM_DEV_VFIO_GROUP_DEL			2
+#define KVM_DEV_TYPE_ARM_VGIC_V2	5
 
 /*
  * ioctls for VM fds
-- 
1.9.0

  parent reply	other threads:[~2014-02-26 18:02 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-02-26 18:01 [Qemu-devel] [PULL 00/45] target-arm queue Peter Maydell
2014-02-26 18:01 ` [Qemu-devel] [PULL 01/45] hw/misc/arm_sysctl: Fix bad boundary check on mb clock accesses Peter Maydell
2014-02-26 18:01 ` [Qemu-devel] [PULL 02/45] hw/net/stellaris_enet: Avoid unintended sign extension Peter Maydell
2014-02-26 18:01 ` [Qemu-devel] [PULL 03/45] hw/timer/arm_timer: Avoid array overrun for bad addresses Peter Maydell
2014-02-26 18:01 ` [Qemu-devel] [PULL 04/45] target-arm: Fix incorrect arithmetic constructing short-form PAR for ATS ops Peter Maydell
2014-02-26 18:01 ` [Qemu-devel] [PULL 05/45] hw/intc/exynos4210_combiner: Don't overrun output_irq array in init Peter Maydell
2014-02-26 18:01 ` [Qemu-devel] [PULL 06/45] hw/arm/musicpal: Remove nonexistent CDTP2, CDTP3 registers Peter Maydell
2014-02-26 18:01 ` [Qemu-devel] [PULL 07/45] target-arm: Load correct access bits from ARMv5 level 2 page table descriptors Peter Maydell
2014-02-26 18:01 ` [Qemu-devel] [PULL 08/45] hw/intc/arm_gic: Fix GIC_SET_LEVEL Peter Maydell
2014-02-26 18:01 ` Peter Maydell [this message]
2014-02-26 18:02 ` [Qemu-devel] [PULL 10/45] kvm: Introduce kvm_arch_irqchip_create Peter Maydell
2014-02-26 18:02 ` [Qemu-devel] [PULL 11/45] kvm: Common device control API functions Peter Maydell
2014-02-26 18:02 ` [Qemu-devel] [PULL 12/45] arm: vgic device control api support Peter Maydell
2014-02-26 18:02 ` [Qemu-devel] [PULL 13/45] hw: arm_gic_kvm: Add KVM VGIC save/restore logic Peter Maydell
2014-02-26 18:02 ` [Qemu-devel] [PULL 14/45] target-arm: Fix raw read and write functions on AArch64 registers Peter Maydell
2014-02-26 18:02 ` [Qemu-devel] [PULL 15/45] target-arm: A64: Make cache ID registers visible to AArch64 Peter Maydell
2014-02-26 18:02 ` [Qemu-devel] [PULL 16/45] target-arm: Implement AArch64 CurrentEL sysreg Peter Maydell
2014-02-26 18:02 ` [Qemu-devel] [PULL 17/45] target-arm: Implement AArch64 MIDR_EL1 Peter Maydell
2014-02-26 18:02 ` [Qemu-devel] [PULL 18/45] target-arm: Implement AArch64 cache invalidate/clean ops Peter Maydell
2014-02-26 18:02 ` [Qemu-devel] [PULL 19/45] target-arm: Implement AArch64 TLB invalidate ops Peter Maydell
2014-02-26 18:02 ` [Qemu-devel] [PULL 20/45] target-arm: Implement AArch64 dummy MDSCR_EL1 Peter Maydell
2014-02-26 18:02 ` [Qemu-devel] [PULL 21/45] target-arm: Implement AArch64 memory attribute registers Peter Maydell
2014-02-26 18:02 ` [Qemu-devel] [PULL 22/45] target-arm: Implement AArch64 SCTLR_EL1 Peter Maydell
2014-02-26 18:02 ` [Qemu-devel] [PULL 23/45] target-arm: Implement AArch64 TCR_EL1 Peter Maydell
2014-02-26 18:02 ` [Qemu-devel] [PULL 24/45] target-arm: Implement AArch64 VBAR_EL1 Peter Maydell
2014-02-26 18:02 ` [Qemu-devel] [PULL 25/45] target-arm: Implement AArch64 TTBR* Peter Maydell
2014-02-26 18:02 ` [Qemu-devel] [PULL 26/45] target-arm: Implement AArch64 MPIDR Peter Maydell
2014-02-26 18:02 ` [Qemu-devel] [PULL 27/45] target-arm: Implement AArch64 generic timers Peter Maydell
2014-02-26 18:02 ` [Qemu-devel] [PULL 28/45] target-arm: Implement AArch64 ID and feature registers Peter Maydell
2014-02-26 18:02 ` [Qemu-devel] [PULL 29/45] target-arm: Implement AArch64 dummy breakpoint and watchpoint registers Peter Maydell
2014-02-26 18:02 ` [Qemu-devel] [PULL 30/45] target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI Peter Maydell
2014-02-26 18:02 ` [Qemu-devel] [PULL 31/45] target-arm: Get MMU index information correct for A64 code Peter Maydell
2014-02-26 18:02 ` [Qemu-devel] [PULL 32/45] target-arm: A64: Implement WFI Peter Maydell
2014-02-26 18:02 ` [Qemu-devel] [PULL 33/45] target-arm: Store AIF bits in env->pstate for AArch32 Peter Maydell
2014-02-26 18:02 ` [Qemu-devel] [PULL 34/45] target-arm: A64: Implement MSR (immediate) instructions Peter Maydell
2014-02-26 18:02 ` [Qemu-devel] [PULL 35/45] target-arm: Implement AArch64 view of CPACR Peter Maydell
2014-02-26 18:02 ` [Qemu-devel] [PULL 36/45] target-arm: Add utility function for checking AA32/64 state of an EL Peter Maydell
2014-02-26 18:02 ` [Qemu-devel] [PULL 37/45] include/qemu/crc32c.h: Rename include guards to match filename Peter Maydell
2014-02-26 18:02 ` [Qemu-devel] [PULL 38/45] target-arm: Add support for AArch32 ARMv8 CRC32 instructions Peter Maydell
2014-02-26 18:02 ` [Qemu-devel] [PULL 39/45] dma/pl330: Delete overly verbose debug printf Peter Maydell
2014-02-26 18:02 ` [Qemu-devel] [PULL 40/45] dma/pl330: Fix misleading type Peter Maydell
2014-02-26 18:02 ` [Qemu-devel] [PULL 41/45] dma/pl330: printf format type sweep Peter Maydell
2014-02-26 18:02 ` [Qemu-devel] [PULL 42/45] dma/pl330: Rename parent_obj Peter Maydell
2014-02-26 18:02 ` [Qemu-devel] [PULL 43/45] dma/pl330: Add event debugging printfs Peter Maydell
2014-02-26 18:02 ` [Qemu-devel] [PULL 44/45] dma/pl330: Fix buffer depth Peter Maydell
2014-02-26 18:02 ` [Qemu-devel] [PULL 45/45] dma/pl330: implement dmaadnh instruction Peter Maydell
2014-02-27 11:33 ` [Qemu-devel] [PULL 00/45] target-arm queue Peter Maydell

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