From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34103) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WIiom-0000rv-Eh for qemu-devel@nongnu.org; Wed, 26 Feb 2014 13:02:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WIiol-0007Nc-Jf for qemu-devel@nongnu.org; Wed, 26 Feb 2014 13:02:52 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:46191) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WIiol-0007Eu-9v for qemu-devel@nongnu.org; Wed, 26 Feb 2014 13:02:51 -0500 From: Peter Maydell Date: Wed, 26 Feb 2014 18:02:16 +0000 Message-Id: <1393437755-23586-27-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1393437755-23586-1-git-send-email-peter.maydell@linaro.org> References: <1393437755-23586-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 26/45] target-arm: Implement AArch64 MPIDR List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anthony Liguori Cc: Blue Swirl , qemu-devel@nongnu.org, Aurelien Jarno Implement the AArch64 MPIDR system register. Signed-off-by: Peter Maydell Reviewed-by: Peter Crosthwaite --- target-arm/helper.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 9dcdf8e..de70a92 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1435,7 +1435,8 @@ static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) { CPUState *cs = CPU(arm_env_get_cpu(env)); uint32_t mpidr = cs->cpu_index; - /* We don't support setting cluster ID ([8..11]) + /* We don't support setting cluster ID ([8..11]) (known as Aff1 + * in later ARM ARM versions), or any of the higher affinity level fields, * so these bits always RAZ. */ if (arm_feature(env, ARM_FEATURE_V7MP)) { @@ -1450,7 +1451,8 @@ static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) } static const ARMCPRegInfo mpidr_cp_reginfo[] = { - { .name = "MPIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5, + { .name = "MPIDR", .state = ARM_CP_STATE_BOTH, + .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5, .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_MIGRATE }, REGINFO_SENTINEL }; -- 1.9.0