From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56002) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WK737-0008Ew-TB for qemu-devel@nongnu.org; Sun, 02 Mar 2014 09:07:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WK72z-0003Qq-8o for qemu-devel@nongnu.org; Sun, 02 Mar 2014 09:07:25 -0500 Received: from mail-ea0-x22c.google.com ([2a00:1450:4013:c01::22c]:50342) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WK72z-0003QU-2n for qemu-devel@nongnu.org; Sun, 02 Mar 2014 09:07:17 -0500 Received: by mail-ea0-f172.google.com with SMTP id l9so3783034eaj.17 for ; Sun, 02 Mar 2014 06:07:16 -0800 (PST) From: Beniamino Galvani Date: Sun, 2 Mar 2014 15:06:36 +0100 Message-Id: <1393769202-4551-3-git-send-email-b.galvani@gmail.com> In-Reply-To: <1393769202-4551-1-git-send-email-b.galvani@gmail.com> References: <1393769202-4551-1-git-send-email-b.galvani@gmail.com> Subject: [Qemu-devel] [PATCH v2 2/7] allwinner-a10-pic: update pending register when an irq is cleared List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Beniamino Galvani , Peter Maydell , Peter Crosthwaite , Li Guang The value of pending register was updated only when an irq was raised from a device; it should also be updated when an interrupt is cleared. Signed-off-by: Beniamino Galvani --- hw/intc/allwinner-a10-pic.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/intc/allwinner-a10-pic.c b/hw/intc/allwinner-a10-pic.c index 00f3c11..9011c82 100644 --- a/hw/intc/allwinner-a10-pic.c +++ b/hw/intc/allwinner-a10-pic.c @@ -49,6 +49,8 @@ static void aw_a10_pic_set_irq(void *opaque, int irq, int level) if (level) { set_bit(irq % 32, (void *)&s->irq_pending[irq / 32]); + } else { + clear_bit(irq % 32, (void *)&s->irq_pending[irq / 32]); } aw_a10_pic_update(s); } -- 1.7.10.4