From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56048) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WK73B-0008Gc-RE for qemu-devel@nongnu.org; Sun, 02 Mar 2014 09:07:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WK733-0003Sf-EM for qemu-devel@nongnu.org; Sun, 02 Mar 2014 09:07:29 -0500 Received: from mail-ee0-x22f.google.com ([2a00:1450:4013:c00::22f]:46175) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WK733-0003SU-7g for qemu-devel@nongnu.org; Sun, 02 Mar 2014 09:07:21 -0500 Received: by mail-ee0-f47.google.com with SMTP id b15so621056eek.20 for ; Sun, 02 Mar 2014 06:07:20 -0800 (PST) From: Beniamino Galvani Date: Sun, 2 Mar 2014 15:06:38 +0100 Message-Id: <1393769202-4551-5-git-send-email-b.galvani@gmail.com> In-Reply-To: <1393769202-4551-1-git-send-email-b.galvani@gmail.com> References: <1393769202-4551-1-git-send-email-b.galvani@gmail.com> Subject: [Qemu-devel] [PATCH v2 4/7] allwinner-a10-pit: use level triggered interrupts List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Beniamino Galvani , Peter Maydell , Peter Crosthwaite , Li Guang Convert the interrupt generation logic to the use of level triggered interrupts. Signed-off-by: Beniamino Galvani --- hw/timer/allwinner-a10-pit.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index 3e1c183..4723b25 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -24,6 +24,15 @@ typedef struct TimerContext { int index; } TimerContext; +static void a10_pit_update_irq(AwA10PITState *s) +{ + int i; + + for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { + qemu_set_irq(s->irq[i], s->irq_status & s->irq_enable & (1 << i)); + } +} + static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size) { AwA10PITState *s = AW_A10_PIT(opaque); @@ -79,9 +88,11 @@ static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value, switch (offset) { case AW_A10_PIT_TIMER_IRQ_EN: s->irq_enable = value; + a10_pit_update_irq(s); break; case AW_A10_PIT_TIMER_IRQ_ST: s->irq_status &= ~value; + a10_pit_update_irq(s); break; case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END: index = offset & 0xf0; @@ -208,7 +219,7 @@ static void a10_pit_timer_cb(void *opaque) ptimer_stop(s->timer[i]); s->control[i] &= ~AW_A10_PIT_TIMER_EN; } - qemu_irq_pulse(s->irq[i]); + a10_pit_update_irq(s); } } -- 1.7.10.4