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From: Beniamino Galvani <b.galvani@gmail.com>
To: qemu-devel@nongnu.org
Cc: Beniamino Galvani <b.galvani@gmail.com>,
	Peter Maydell <peter.maydell@linaro.org>,
	Peter Crosthwaite <peter.crosthwaite@xilinx.com>,
	Li Guang <lig.fnst@cn.fujitsu.com>
Subject: [Qemu-devel] [PATCH v2 7/7] allwinner-emac: update irq status after writes to interrupt registers
Date: Sun,  2 Mar 2014 15:06:41 +0100	[thread overview]
Message-ID: <1393769202-4551-8-git-send-email-b.galvani@gmail.com> (raw)
In-Reply-To: <1393769202-4551-1-git-send-email-b.galvani@gmail.com>

The irq line status must be updated after writes to the INT_CTL and
INT_STA registers.

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
---
 hw/net/allwinner_emac.c |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/hw/net/allwinner_emac.c b/hw/net/allwinner_emac.c
index 91931ac..d780ba0 100644
--- a/hw/net/allwinner_emac.c
+++ b/hw/net/allwinner_emac.c
@@ -391,9 +391,11 @@ static void aw_emac_write(void *opaque, hwaddr offset, uint64_t value,
         break;
     case EMAC_INT_CTL_REG:
         s->int_ctl = value;
+        aw_emac_update_irq(s);
         break;
     case EMAC_INT_STA_REG:
         s->int_sta &= ~value;
+        aw_emac_update_irq(s);
         break;
     case EMAC_MAC_MADR_REG:
         s->phy_target = value;
-- 
1.7.10.4

  parent reply	other threads:[~2014-03-02 14:07 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-03-02 14:06 [Qemu-devel] [PATCH v2 0/7] Allwinner A10 fixes Beniamino Galvani
2014-03-02 14:06 ` [Qemu-devel] [PATCH v2 1/7] allwinner-a10-pic: set vector address when an interrupt is pending Beniamino Galvani
2014-03-03 11:16   ` Peter Crosthwaite
2014-03-03 22:14     ` Beniamino Galvani
2014-03-02 14:06 ` [Qemu-devel] [PATCH v2 2/7] allwinner-a10-pic: update pending register when an irq is cleared Beniamino Galvani
2014-03-03 11:56   ` Peter Crosthwaite
2014-03-03 22:09     ` Beniamino Galvani
2014-03-02 14:06 ` [Qemu-devel] [PATCH v2 3/7] allwinner-a10-pit: avoid generation of spurious interrupts Beniamino Galvani
2014-03-03 11:08   ` Peter Crosthwaite
2014-03-03 22:16     ` Beniamino Galvani
2014-03-04 11:30       ` Peter Crosthwaite
2014-03-02 14:06 ` [Qemu-devel] [PATCH v2 4/7] allwinner-a10-pit: use level triggered interrupts Beniamino Galvani
2014-03-02 14:06 ` [Qemu-devel] [PATCH v2 5/7] allwinner-a10-pit: implement prescaler and source selection Beniamino Galvani
2014-03-03 10:57   ` Peter Crosthwaite
2014-03-03 22:25     ` Beniamino Galvani
2014-03-02 14:06 ` [Qemu-devel] [PATCH v2 6/7] allwinner-emac: set autonegotiation complete bit on link up Beniamino Galvani
2014-03-02 14:06 ` Beniamino Galvani [this message]
2014-03-03 10:59   ` [Qemu-devel] [PATCH v2 7/7] allwinner-emac: update irq status after writes to interrupt registers Peter Crosthwaite

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