From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58673) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WLhoK-00016L-Gw for qemu-devel@nongnu.org; Thu, 06 Mar 2014 18:35:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WLhnx-0003LO-H2 for qemu-devel@nongnu.org; Thu, 06 Mar 2014 18:34:44 -0500 From: Alexander Graf Date: Fri, 7 Mar 2014 00:33:14 +0100 Message-Id: <1394148857-19607-68-git-send-email-agraf@suse.de> In-Reply-To: <1394148857-19607-1-git-send-email-agraf@suse.de> References: <1394148857-19607-1-git-send-email-agraf@suse.de> Subject: [Qemu-devel] [PULL 067/130] target-ppc: Add ISA 2.06 ftsqrt List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Tom Musta , blauwirbel@gmail.com, qemu-ppc@nongnu.org, aliguori@amazon.com, aurelien@aurel32.net From: Tom Musta This patch adds the Floating Point Test for Square Root instruction which was introduced in Power ISA 2.06. Signed-off-by: Tom Musta Reviewed-by: Richard Henderson Signed-off-by: Alexander Graf --- target-ppc/fpu_helper.c | 31 +++++++++++++++++++++++++++++++ target-ppc/helper.h | 1 + target-ppc/translate.c | 10 ++++++++++ 3 files changed, 42 insertions(+) diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c index 772b135..4ef3e2f 100644 --- a/target-ppc/fpu_helper.c +++ b/target-ppc/fpu_helper.c @@ -1039,6 +1039,37 @@ uint32_t helper_ftdiv(uint64_t fra, uint64_t frb) return 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); } +uint32_t helper_ftsqrt(uint64_t frb) +{ + int fe_flag = 0; + int fg_flag = 0; + + if (unlikely(float64_is_infinity(frb) || float64_is_zero(frb))) { + fe_flag = 1; + fg_flag = 1; + } else { + int e_b = ppc_float64_get_unbiased_exp(frb); + + if (unlikely(float64_is_any_nan(frb))) { + fe_flag = 1; + } else if (unlikely(float64_is_zero(frb))) { + fe_flag = 1; + } else if (unlikely(float64_is_neg(frb))) { + fe_flag = 1; + } else if (!float64_is_zero(frb) && (e_b <= (-1022+52))) { + fe_flag = 1; + } + + if (unlikely(float64_is_zero_or_denormal(frb))) { + /* XB is not zero because of the above check and */ + /* therefore must be denormalized. */ + fg_flag = 1; + } + } + + return 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); +} + void helper_fcmpu(CPUPPCState *env, uint64_t arg1, uint64_t arg2, uint32_t crfD) { diff --git a/target-ppc/helper.h b/target-ppc/helper.h index 2fb337c..a4480e8 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -100,6 +100,7 @@ DEF_HELPER_2(frsqrte, i64, env, i64) DEF_HELPER_4(fsel, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_2(ftdiv, TCG_CALL_NO_RWG_SE, i32, i64, i64) +DEF_HELPER_FLAGS_1(ftsqrt, TCG_CALL_NO_RWG_SE, i32, i64) #define dh_alias_avr ptr #define dh_ctype_avr ppc_avr_t * diff --git a/target-ppc/translate.c b/target-ppc/translate.c index f372742..c9aebc5 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -2248,6 +2248,15 @@ static void gen_ftdiv(DisasContext *ctx) cpu_fpr[rB(ctx->opcode)]); } +static void gen_ftsqrt(DisasContext *ctx) +{ + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); +} + /*** Floating-Point compare ***/ @@ -9869,6 +9878,7 @@ GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT), GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT), GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT), GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206), +GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206), GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT), GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206), GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT), -- 1.8.1.4