From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58834) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WLhoU-0001B5-0X for qemu-devel@nongnu.org; Thu, 06 Mar 2014 18:35:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WLhny-0003O4-C8 for qemu-devel@nongnu.org; Thu, 06 Mar 2014 18:34:53 -0500 From: Alexander Graf Date: Fri, 7 Mar 2014 00:33:38 +0100 Message-Id: <1394148857-19607-92-git-send-email-agraf@suse.de> In-Reply-To: <1394148857-19607-1-git-send-email-agraf@suse.de> References: <1394148857-19607-1-git-send-email-agraf@suse.de> Subject: [Qemu-devel] [PULL 091/130] target-ppc: Altivec 2.07: Add Instruction Flag List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Tom Musta , blauwirbel@gmail.com, qemu-ppc@nongnu.org, aliguori@amazon.com, aurelien@aurel32.net From: Tom Musta This patch adds a flag that will be used to tag the Altivec instructions introduced in Power ISA Version 2.07. The flag is added to Power8 model since P8 supports these instructions. Signed-off-by: Tom Musta Signed-off-by: Alexander Graf --- target-ppc/cpu.h | 5 ++++- target-ppc/translate_init.c | 2 +- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 7cf7255..88c2788 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1893,12 +1893,15 @@ enum { PPC2_BCTAR_ISA207 = 0x0000000000001000ULL, /* ISA 2.07 load/store quadword */ PPC2_LSQ_ISA207 = 0x0000000000002000ULL, + /* ISA 2.07 Altivec */ + PPC2_ALTIVEC_207 = 0x0000000000004000ULL, #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \ PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \ PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \ - PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207) + PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \ + PPC2_ALTIVEC_207) }; /*****************************************************************************/ diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index b9576ac..9dd8c1c 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -7172,7 +7172,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | - PPC2_LSQ_ISA207; + PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207; pcc->msr_mask = 0x800000000284FF36ULL; pcc->mmu_model = POWERPC_MMU_2_06; #if defined(CONFIG_SOFTMMU) -- 1.8.1.4