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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Peter Crosthwaite" <peter.crosthwaite@xilinx.com>,
	patches@linaro.org, "Michael Matz" <matz@suse.de>,
	"Alexander Graf" <agraf@suse.de>,
	"Will Newton" <will.newton@linaro.org>,
	"Dirk Mueller" <dmueller@suse.de>,
	"Laurent Desnogues" <laurent.desnogues@gmail.com>,
	"Alex Bennée" <alex.bennee@linaro.org>,
	kvmarm@lists.cs.columbia.edu,
	"Christoffer Dall" <christoffer.dall@linaro.org>,
	"Richard Henderson" <rth@twiddle.net>
Subject: [Qemu-devel] [PATCH 04/16] target-arm: A64: Add FSQRT to C3.6.17 (two misc)
Date: Sun,  9 Mar 2014 15:10:55 +0000	[thread overview]
Message-ID: <1394377867-7115-5-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1394377867-7115-1-git-send-email-peter.maydell@linaro.org>

From: Alex Bennée <alex.bennee@linaro.org>

Implement FSQRT in the two-reg-misc category.
GCC uses this instruction form.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/translate-a64.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index da4063b..8313f7f 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -6623,6 +6623,9 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
     case 0x6f: /* FNEG */
         gen_helper_vfp_negd(tcg_rd, tcg_rn);
         break;
+    case 0x7f: /* FSQRT */
+        gen_helper_vfp_sqrtd(tcg_rd, tcg_rn, cpu_env);
+        break;
     default:
         g_assert_not_reached();
     }
@@ -8392,6 +8395,12 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
             }
             handle_2misc_fcmp_zero(s, opcode, false, u, is_q, size, rn, rd);
             return;
+        case 0x7f: /* FSQRT */
+            if (size == 3 && !is_q) {
+                unallocated_encoding(s);
+                return;
+            }
+            break;
         case 0x16: /* FCVTN, FCVTN2 */
         case 0x17: /* FCVTL, FCVTL2 */
         case 0x18: /* FRINTN */
@@ -8416,7 +8425,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
         case 0x7b: /* FCVTZU */
         case 0x7c: /* URSQRTE */
         case 0x7d: /* FRSQRTE */
-        case 0x7f: /* FSQRT */
             unsupported_encoding(s, insn);
             return;
         default:
@@ -8493,6 +8501,9 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
                 case 0x6f: /* FNEG */
                     gen_helper_vfp_negs(tcg_res, tcg_op);
                     break;
+                case 0x7f: /* FSQRT */
+                    gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env);
+                    break;
                 default:
                     g_assert_not_reached();
                 }
-- 
1.9.0

  parent reply	other threads:[~2014-03-09 15:11 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-03-09 15:10 [Qemu-devel] [PATCH 00/16] A64 Neon patches: sixth set Peter Maydell
2014-03-09 15:10 ` [Qemu-devel] [PATCH 01/16] target-arm: A64: Implement PMULL instruction Peter Maydell
2014-03-09 15:10 ` [Qemu-devel] [PATCH 02/16] target-arm: A64: Fix bug in add_sub_ext handling of rn Peter Maydell
2014-03-13  8:04   ` Laurent Desnogues
2014-03-09 15:10 ` [Qemu-devel] [PATCH 03/16] target-arm: A64: Add last AdvSIMD Integer to FP ops Peter Maydell
2014-03-09 15:10 ` Peter Maydell [this message]
2014-03-09 15:10 ` [Qemu-devel] [PATCH 05/16] target-arm: A64: Add remaining CLS/Z vector ops Peter Maydell
2014-03-09 15:10 ` [Qemu-devel] [PATCH 06/16] target-arm: A64: Saturating and narrowing shift ops Peter Maydell
2014-03-10 15:34   ` Janne Grunau
2014-03-09 15:10 ` [Qemu-devel] [PATCH 07/16] target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALP Peter Maydell
2014-03-09 15:10 ` [Qemu-devel] [PATCH 08/16] target-arm: A64: Implement SHLL, SHLL2 Peter Maydell
2014-03-09 15:11 ` [Qemu-devel] [PATCH 09/16] target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructions Peter Maydell
2014-03-11 13:53   ` Peter Maydell
2014-03-09 15:11 ` [Qemu-devel] [PATCH 10/16] target-arm: A64: Implement FCVTN Peter Maydell
2014-03-09 15:11 ` [Qemu-devel] [PATCH 11/16] target-arm: A64: Implement FCVTL Peter Maydell
2014-03-09 15:11 ` [Qemu-devel] [PATCH 12/16] target-arm: A64: List unsupported shift-imm opcodes Peter Maydell
2014-03-09 15:11 ` [Qemu-devel] [PATCH 13/16] target-arm: A64: Add FRECPX (reciprocal exponent) Peter Maydell
2014-03-09 15:11 ` [Qemu-devel] [PATCH 14/16] target-arm: A64: Implement SRI Peter Maydell
2014-03-09 15:11 ` [Qemu-devel] [PATCH 15/16] target-arm: A64: Implement FRINT* Peter Maydell
2014-03-09 15:11 ` [Qemu-devel] [PATCH 16/16] exec-all.h: Increase MAX_OP_PER_INSTR for ARM A64 decoder Peter Maydell
2014-03-10 13:24   ` Michael Matz
2014-03-10 13:27     ` Peter Maydell

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