From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38937) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WMfNx-0004JT-W1 for qemu-devel@nongnu.org; Sun, 09 Mar 2014 11:11:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WMfNw-0004zt-RI for qemu-devel@nongnu.org; Sun, 09 Mar 2014 11:11:29 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:46487) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WMfNw-0004x2-JQ for qemu-devel@nongnu.org; Sun, 09 Mar 2014 11:11:28 -0400 From: Peter Maydell Date: Sun, 9 Mar 2014 15:10:55 +0000 Message-Id: <1394377867-7115-5-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1394377867-7115-1-git-send-email-peter.maydell@linaro.org> References: <1394377867-7115-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH 04/16] target-arm: A64: Add FSQRT to C3.6.17 (two misc) List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Crosthwaite , patches@linaro.org, Michael Matz , Alexander Graf , Will Newton , Dirk Mueller , Laurent Desnogues , =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvmarm@lists.cs.columbia.edu, Christoffer Dall , Richard Henderson From: Alex Bennée Implement FSQRT in the two-reg-misc category. GCC uses this instruction form. Signed-off-by: Alex Bennée Signed-off-by: Peter Maydell --- target-arm/translate-a64.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index da4063b..8313f7f 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -6623,6 +6623,9 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u, case 0x6f: /* FNEG */ gen_helper_vfp_negd(tcg_rd, tcg_rn); break; + case 0x7f: /* FSQRT */ + gen_helper_vfp_sqrtd(tcg_rd, tcg_rn, cpu_env); + break; default: g_assert_not_reached(); } @@ -8392,6 +8395,12 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) } handle_2misc_fcmp_zero(s, opcode, false, u, is_q, size, rn, rd); return; + case 0x7f: /* FSQRT */ + if (size == 3 && !is_q) { + unallocated_encoding(s); + return; + } + break; case 0x16: /* FCVTN, FCVTN2 */ case 0x17: /* FCVTL, FCVTL2 */ case 0x18: /* FRINTN */ @@ -8416,7 +8425,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) case 0x7b: /* FCVTZU */ case 0x7c: /* URSQRTE */ case 0x7d: /* FRSQRTE */ - case 0x7f: /* FSQRT */ unsupported_encoding(s, insn); return; default: @@ -8493,6 +8501,9 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) case 0x6f: /* FNEG */ gen_helper_vfp_negs(tcg_res, tcg_op); break; + case 0x7f: /* FSQRT */ + gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env); + break; default: g_assert_not_reached(); } -- 1.9.0