From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48266) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WNrbV-0007OO-Gi for qemu-devel@nongnu.org; Wed, 12 Mar 2014 18:26:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WNrbP-0007ZT-N7 for qemu-devel@nongnu.org; Wed, 12 Mar 2014 18:26:25 -0400 Received: from mail-qa0-x22a.google.com ([2607:f8b0:400d:c00::22a]:60847) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WNrbP-0007ZO-JY for qemu-devel@nongnu.org; Wed, 12 Mar 2014 18:26:19 -0400 Received: by mail-qa0-f42.google.com with SMTP id k15so194730qaq.15 for ; Wed, 12 Mar 2014 15:26:19 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Wed, 12 Mar 2014 15:25:46 -0700 Message-Id: <1394663146-24552-1-git-send-email-rth@twiddle.net> In-Reply-To: <1394480575-3698-2-git-send-email-mst@redhat.com> References: <1394480575-3698-2-git-send-email-mst@redhat.com> Subject: [Qemu-devel] [PATCH] hw/i386: Use unaligned store functions building acpi tables List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, aliguori@amazon.com, mst@redhat.com Hosts that don't support native unaligned stores will SIGBUS without additional help. Signed-off-by: Richard Henderson --- hw/i386/acpi-build.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index b1a7ebb..d636115 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -886,22 +886,24 @@ static void build_pci_bus_end(PCIBus *bus, void *bus_state) static void patch_pci_windows(PcPciInfo *pci, uint8_t *start, unsigned size) { - *ACPI_BUILD_PTR(start, size, acpi_pci32_start[0], uint32_t) = - cpu_to_le32(pci->w32.begin); + /* Note that these pointers are unaligned, so we must use routines + that take care for unaligned stores on the host. */ - *ACPI_BUILD_PTR(start, size, acpi_pci32_end[0], uint32_t) = - cpu_to_le32(pci->w32.end - 1); + stl_le_p(ACPI_BUILD_PTR(start, size, acpi_pci32_start[0], uint32_t), + pci->w32.begin); + stl_le_p(ACPI_BUILD_PTR(start, size, acpi_pci32_end[0], uint32_t), + pci->w32.end - 1); if (pci->w64.end || pci->w64.begin) { - *ACPI_BUILD_PTR(start, size, acpi_pci64_valid[0], uint8_t) = 1; - *ACPI_BUILD_PTR(start, size, acpi_pci64_start[0], uint64_t) = - cpu_to_le64(pci->w64.begin); - *ACPI_BUILD_PTR(start, size, acpi_pci64_end[0], uint64_t) = - cpu_to_le64(pci->w64.end - 1); - *ACPI_BUILD_PTR(start, size, acpi_pci64_length[0], uint64_t) = - cpu_to_le64(pci->w64.end - pci->w64.begin); + stb_p(ACPI_BUILD_PTR(start, size, acpi_pci64_valid[0], uint8_t), 1); + stq_le_p(ACPI_BUILD_PTR(start, size, acpi_pci64_start[0], uint64_t), + pci->w64.begin); + stq_le_p(ACPI_BUILD_PTR(start, size, acpi_pci64_end[0], uint64_t), + pci->w64.end - 1); + stq_le_p(ACPI_BUILD_PTR(start, size, acpi_pci64_length[0], uint64_t), + pci->w64.end - pci->w64.begin); } else { - *ACPI_BUILD_PTR(start, size, acpi_pci64_valid[0], uint8_t) = 0; + stb_p(ACPI_BUILD_PTR(start, size, acpi_pci64_valid[0], uint8_t), 0); } } @@ -930,8 +932,7 @@ build_ssdt(GArray *table_data, GArray *linker, patch_pci_windows(pci, ssdt_ptr, sizeof(ssdp_misc_aml)); - *(uint16_t *)(ssdt_ptr + *ssdt_isa_pest) = - cpu_to_le16(misc->pvpanic_port); + stw_le_p(ssdt_ptr + *ssdt_isa_pest, misc->pvpanic_port); { GArray *sb_scope = build_alloc_array(); -- 1.8.5.3