From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50596) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WO72Y-0005MT-6J for qemu-devel@nongnu.org; Thu, 13 Mar 2014 10:55:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WO72R-0005wC-Vw for qemu-devel@nongnu.org; Thu, 13 Mar 2014 10:55:22 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Thu, 13 Mar 2014 15:54:13 +0100 Message-Id: <1394722501-32326-11-git-send-email-afaerber@suse.de> In-Reply-To: <1394722501-32326-1-git-send-email-afaerber@suse.de> References: <1394722501-32326-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PULL for-2.0-rc0 10/58] cpu: Turn cpu_has_work() into a CPUClass hook List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Jia Liu , Anthony Green , Alexander Graf , Blue Swirl , Max Filippov , Michael Walle , "open list:PowerPC" , "Edgar E. Iglesias" , Guan Xuetao , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Aurelien Jarno , Richard Henderson Default to false. Tidy variable naming and inline cast uses while at it. Tested-by: Jia Liu (or32) Signed-off-by: Andreas F=C3=A4rber --- cpu-exec.c | 5 ----- cpus.c | 2 +- include/qom/cpu.h | 12 ++++++++++-- qom/cpu.c | 6 ++++++ target-alpha/cpu.c | 16 ++++++++++++++++ target-alpha/cpu.h | 15 --------------- target-arm/cpu.c | 7 +++++++ target-arm/cpu.h | 6 ------ target-cris/cpu.c | 6 ++++++ target-cris/cpu.h | 5 ----- target-i386/cpu.c | 15 +++++++++++++++ target-i386/cpu.h | 14 -------------- target-lm32/cpu.c | 6 ++++++ target-lm32/cpu.h | 5 ----- target-m68k/cpu.c | 6 ++++++ target-m68k/cpu.h | 5 ----- target-microblaze/cpu.c | 6 ++++++ target-microblaze/cpu.h | 5 ----- target-mips/cpu.c | 30 ++++++++++++++++++++++++++++++ target-mips/cpu.h | 28 ---------------------------- target-moxie/cpu.c | 6 ++++++ target-moxie/cpu.h | 5 ----- target-openrisc/cpu.c | 7 +++++++ target-openrisc/cpu.h | 5 ----- target-ppc/cpu.h | 8 -------- target-ppc/translate_init.c | 9 +++++++++ target-s390x/cpu.c | 10 ++++++++++ target-s390x/cpu.h | 9 --------- target-sh4/cpu.c | 6 ++++++ target-sh4/cpu.h | 5 ----- target-sparc/cpu.c | 10 ++++++++++ target-sparc/cpu.h | 9 --------- target-unicore32/cpu.c | 7 +++++++ target-unicore32/cpu.h | 6 ------ target-xtensa/cpu.c | 8 ++++++++ target-xtensa/cpu.h | 7 ------- 36 files changed, 172 insertions(+), 145 deletions(-) diff --git a/cpu-exec.c b/cpu-exec.c index 1b0f617..6559d5e 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -23,11 +23,6 @@ #include "qemu/atomic.h" #include "sysemu/qtest.h" =20 -bool qemu_cpu_has_work(CPUState *cpu) -{ - return cpu_has_work(cpu); -} - void cpu_loop_exit(CPUArchState *env) { CPUState *cpu =3D ENV_GET_CPU(env); diff --git a/cpus.c b/cpus.c index b6421fd..eda6d02 100644 --- a/cpus.c +++ b/cpus.c @@ -76,7 +76,7 @@ static bool cpu_thread_is_idle(CPUState *cpu) if (cpu_is_stopped(cpu)) { return true; } - if (!cpu->halted || qemu_cpu_has_work(cpu) || + if (!cpu->halted || cpu_has_work(cpu) || kvm_halt_in_kernel()) { return false; } diff --git a/include/qom/cpu.h b/include/qom/cpu.h index d734be8..89d5dd1 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -70,6 +70,7 @@ struct TranslationBlock; * instantiatable CPU type. * @reset: Callback to reset the #CPUState to its initial state. * @reset_dump_flags: #CPUDumpFlags to use for reset logging. + * @has_work: Callback for checking if there is work to do. * @do_interrupt: Callback for interrupt handling. * @do_unassigned_access: Callback for unassigned access handling. * @memory_rw_debug: Callback for GDB memory access. @@ -99,6 +100,7 @@ typedef struct CPUClass { =20 void (*reset)(CPUState *cpu); int reset_dump_flags; + bool (*has_work)(CPUState *cpu); void (*do_interrupt)(CPUState *cpu); CPUUnassignedAccess do_unassigned_access; int (*memory_rw_debug)(CPUState *cpu, vaddr addr, @@ -348,14 +350,20 @@ void cpu_reset(CPUState *cpu); ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_mod= el); =20 /** - * qemu_cpu_has_work: + * cpu_has_work: * @cpu: The vCPU to check. * * Checks whether the CPU has work to do. * * Returns: %true if the CPU has work, %false otherwise. */ -bool qemu_cpu_has_work(CPUState *cpu); +static inline bool cpu_has_work(CPUState *cpu) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + g_assert(cc->has_work); + return cc->has_work(cpu); +} =20 /** * qemu_cpu_is_self: diff --git a/qom/cpu.c b/qom/cpu.c index 40d82dd..f36d597 100644 --- a/qom/cpu.c +++ b/qom/cpu.c @@ -200,6 +200,11 @@ static void cpu_common_reset(CPUState *cpu) cpu->halted =3D 0; } =20 +static bool cpu_common_has_work(CPUState *cs) +{ + return false; +} + ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_mod= el) { CPUClass *cc =3D CPU_CLASS(object_class_by_name(typename)); @@ -244,6 +249,7 @@ static void cpu_class_init(ObjectClass *klass, void *= data) k->class_by_name =3D cpu_common_class_by_name; k->reset =3D cpu_common_reset; k->get_arch_id =3D cpu_common_get_arch_id; + k->has_work =3D cpu_common_has_work; k->get_paging_enabled =3D cpu_common_get_paging_enabled; k->get_memory_mapping =3D cpu_common_get_memory_mapping; k->write_elf32_qemunote =3D cpu_common_write_elf32_qemunote; diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c index a0d5d5b..cf2a315 100644 --- a/target-alpha/cpu.c +++ b/target-alpha/cpu.c @@ -31,6 +31,21 @@ static void alpha_cpu_set_pc(CPUState *cs, vaddr value= ) cpu->env.pc =3D value; } =20 +static bool alpha_cpu_has_work(CPUState *cs) +{ + /* Here we are checking to see if the CPU should wake up from HALT. + We will have gotten into this state only for WTINT from PALmode. = */ + /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU + asleep even if (some) interrupts have been asserted. For now, + assume that if a CPU really wants to stay asleep, it will mask + interrupts at the chipset level, which will prevent these bits + from being set in the first place. */ + return cs->interrupt_request & (CPU_INTERRUPT_HARD + | CPU_INTERRUPT_TIMER + | CPU_INTERRUPT_SMP + | CPU_INTERRUPT_MCHK); +} + static void alpha_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); @@ -267,6 +282,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, voi= d *data) dc->realize =3D alpha_cpu_realizefn; =20 cc->class_by_name =3D alpha_cpu_class_by_name; + cc->has_work =3D alpha_cpu_has_work; cc->do_interrupt =3D alpha_cpu_do_interrupt; cc->dump_state =3D alpha_cpu_dump_state; cc->set_pc =3D alpha_cpu_set_pc; diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h index c85dc6e..a172124 100644 --- a/target-alpha/cpu.h +++ b/target-alpha/cpu.h @@ -498,21 +498,6 @@ static inline void cpu_get_tb_cpu_state(CPUAlphaStat= e *env, target_ulong *pc, *pflags =3D flags; } =20 -static inline bool cpu_has_work(CPUState *cpu) -{ - /* Here we are checking to see if the CPU should wake up from HALT. - We will have gotten into this state only for WTINT from PALmode. = */ - /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU - asleep even if (some) interrupts have been asserted. For now, - assume that if a CPU really wants to stay asleep, it will mask - interrupts at the chipset level, which will prevent these bits - from being set in the first place. */ - return cpu->interrupt_request & (CPU_INTERRUPT_HARD - | CPU_INTERRUPT_TIMER - | CPU_INTERRUPT_SMP - | CPU_INTERRUPT_MCHK); -} - #include "exec/exec-all.h" =20 #endif /* !defined (__CPU_ALPHA_H__) */ diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 1ce8a9b..d792a91 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -36,6 +36,12 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.regs[15] =3D value; } =20 +static bool arm_cpu_has_work(CPUState *cs) +{ + return cs->interrupt_request & + (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB); +} + static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) { /* Reset a single ARMCPRegInfo register */ @@ -1001,6 +1007,7 @@ static void arm_cpu_class_init(ObjectClass *oc, voi= d *data) cc->reset =3D arm_cpu_reset; =20 cc->class_by_name =3D arm_cpu_class_by_name; + cc->has_work =3D arm_cpu_has_work; cc->do_interrupt =3D arm_cpu_do_interrupt; cc->dump_state =3D arm_cpu_dump_state; cc->set_pc =3D arm_cpu_set_pc; diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 0a7edfe..00d91d1 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -1166,12 +1166,6 @@ static inline void cpu_get_tb_cpu_state(CPUARMStat= e *env, target_ulong *pc, *cs_base =3D 0; } =20 -static inline bool cpu_has_work(CPUState *cpu) -{ - return cpu->interrupt_request & - (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB); -} - #include "exec/exec-all.h" =20 static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb= ) diff --git a/target-cris/cpu.c b/target-cris/cpu.c index 1ac8124..07da845 100644 --- a/target-cris/cpu.c +++ b/target-cris/cpu.c @@ -33,6 +33,11 @@ static void cris_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.pc =3D value; } =20 +static bool cris_cpu_has_work(CPUState *cs) +{ + return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_N= MI); +} + /* CPUClass::reset() */ static void cris_cpu_reset(CPUState *s) { @@ -283,6 +288,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void= *data) cc->reset =3D cris_cpu_reset; =20 cc->class_by_name =3D cris_cpu_class_by_name; + cc->has_work =3D cris_cpu_has_work; cc->do_interrupt =3D cris_cpu_do_interrupt; cc->dump_state =3D cris_cpu_dump_state; cc->set_pc =3D cris_cpu_set_pc; diff --git a/target-cris/cpu.h b/target-cris/cpu.h index 1d7d80d..1287cad 100644 --- a/target-cris/cpu.h +++ b/target-cris/cpu.h @@ -276,11 +276,6 @@ static inline void cpu_get_tb_cpu_state(CPUCRISState= *env, target_ulong *pc, #define cpu_list cris_cpu_list void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf); =20 -static inline bool cpu_has_work(CPUState *cpu) -{ - return cpu->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_= NMI); -} - #include "exec/exec-all.h" =20 #endif diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 5cfe450..5fb8a6d 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -2695,6 +2695,20 @@ static void x86_cpu_synchronize_from_tb(CPUState *= cs, TranslationBlock *tb) cpu->env.eip =3D tb->pc - tb->cs_base; } =20 +static bool x86_cpu_has_work(CPUState *cs) +{ + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; + + return ((cs->interrupt_request & (CPU_INTERRUPT_HARD | + CPU_INTERRUPT_POLL)) && + (env->eflags & IF_MASK)) || + (cs->interrupt_request & (CPU_INTERRUPT_NMI | + CPU_INTERRUPT_INIT | + CPU_INTERRUPT_SIPI | + CPU_INTERRUPT_MCE)); +} + static Property x86_cpu_properties[] =3D { DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), { .name =3D "hv-spinlocks", .info =3D &qdev_prop_spinlocks }, @@ -2721,6 +2735,7 @@ static void x86_cpu_common_class_init(ObjectClass *= oc, void *data) cc->reset =3D x86_cpu_reset; cc->reset_dump_flags =3D CPU_DUMP_FPU | CPU_DUMP_CCOP; =20 + cc->has_work =3D x86_cpu_has_work; cc->do_interrupt =3D x86_cpu_do_interrupt; cc->dump_state =3D x86_cpu_dump_state; cc->set_pc =3D x86_cpu_set_pc; diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 0014acc..4b8c85b 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -1186,20 +1186,6 @@ void optimize_flags_init(void); #include "hw/i386/apic.h" #endif =20 -static inline bool cpu_has_work(CPUState *cs) -{ - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; - - return ((cs->interrupt_request & (CPU_INTERRUPT_HARD | - CPU_INTERRUPT_POLL)) && - (env->eflags & IF_MASK)) || - (cs->interrupt_request & (CPU_INTERRUPT_NMI | - CPU_INTERRUPT_INIT | - CPU_INTERRUPT_SIPI | - CPU_INTERRUPT_MCE)); -} - #include "exec/exec-all.h" =20 static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *= pc, diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c index 7e716fb..c157f52 100644 --- a/target-lm32/cpu.c +++ b/target-lm32/cpu.c @@ -110,6 +110,11 @@ static void lm32_cpu_init_cfg_reg(LM32CPU *cpu) env->cfg =3D cfg; } =20 +static bool lm32_cpu_has_work(CPUState *cs) +{ + return cs->interrupt_request & CPU_INTERRUPT_HARD; +} + /* CPUClass::reset() */ static void lm32_cpu_reset(CPUState *s) { @@ -255,6 +260,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void= *data) cc->reset =3D lm32_cpu_reset; =20 cc->class_by_name =3D lm32_cpu_class_by_name; + cc->has_work =3D lm32_cpu_has_work; cc->do_interrupt =3D lm32_cpu_do_interrupt; cc->dump_state =3D lm32_cpu_dump_state; cc->set_pc =3D lm32_cpu_set_pc; diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h index 18cf348..e6314c0 100644 --- a/target-lm32/cpu.h +++ b/target-lm32/cpu.h @@ -245,11 +245,6 @@ static inline void cpu_get_tb_cpu_state(CPULM32State= *env, target_ulong *pc, *flags =3D 0; } =20 -static inline bool cpu_has_work(CPUState *cpu) -{ - return cpu->interrupt_request & CPU_INTERRUPT_HARD; -} - #include "exec/exec-all.h" =20 #endif diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c index 008d8db..7d66ed0 100644 --- a/target-m68k/cpu.c +++ b/target-m68k/cpu.c @@ -30,6 +30,11 @@ static void m68k_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.pc =3D value; } =20 +static bool m68k_cpu_has_work(CPUState *cs) +{ + return cs->interrupt_request & CPU_INTERRUPT_HARD; +} + static void m68k_set_feature(CPUM68KState *env, int feature) { env->features |=3D (1u << feature); @@ -189,6 +194,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void = *data) cc->reset =3D m68k_cpu_reset; =20 cc->class_by_name =3D m68k_cpu_class_by_name; + cc->has_work =3D m68k_cpu_has_work; cc->do_interrupt =3D m68k_cpu_do_interrupt; cc->dump_state =3D m68k_cpu_dump_state; cc->set_pc =3D m68k_cpu_set_pc; diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h index cfd6846..5f79d2a 100644 --- a/target-m68k/cpu.h +++ b/target-m68k/cpu.h @@ -253,11 +253,6 @@ static inline void cpu_get_tb_cpu_state(CPUM68KState= *env, target_ulong *pc, | ((env->macsr >> 4) & 0xf); /* Bits 0-3 */ } =20 -static inline bool cpu_has_work(CPUState *cpu) -{ - return cpu->interrupt_request & CPU_INTERRUPT_HARD; -} - #include "exec/exec-all.h" =20 #endif diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c index f108c0b..bbda0fd 100644 --- a/target-microblaze/cpu.c +++ b/target-microblaze/cpu.c @@ -34,6 +34,11 @@ static void mb_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.sregs[SR_PC] =3D value; } =20 +static bool mb_cpu_has_work(CPUState *cs) +{ + return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_N= MI); +} + #ifndef CONFIG_USER_ONLY static void microblaze_cpu_set_irq(void *opaque, int irq, int level) { @@ -160,6 +165,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *= data) mcc->parent_reset =3D cc->reset; cc->reset =3D mb_cpu_reset; =20 + cc->has_work =3D mb_cpu_has_work; cc->do_interrupt =3D mb_cpu_do_interrupt; cc->dump_state =3D mb_cpu_dump_state; cc->set_pc =3D mb_cpu_set_pc; diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h index 1df014e..78a7661 100644 --- a/target-microblaze/cpu.h +++ b/target-microblaze/cpu.h @@ -363,11 +363,6 @@ void mb_cpu_unassigned_access(CPUState *cpu, hwaddr = addr, unsigned size); #endif =20 -static inline bool cpu_has_work(CPUState *cpu) -{ - return cpu->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_= NMI); -} - #include "exec/exec-all.h" =20 #endif diff --git a/target-mips/cpu.c b/target-mips/cpu.c index 9dd47e8..0a2dc46 100644 --- a/target-mips/cpu.c +++ b/target-mips/cpu.c @@ -45,6 +45,35 @@ static void mips_cpu_synchronize_from_tb(CPUState *cs,= TranslationBlock *tb) env->hflags |=3D tb->flags & MIPS_HFLAG_BMASK; } =20 +static bool mips_cpu_has_work(CPUState *cs) +{ + MIPSCPU *cpu =3D MIPS_CPU(cs); + CPUMIPSState *env =3D &cpu->env; + bool has_work =3D false; + + /* It is implementation dependent if non-enabled interrupts + wake-up the CPU, however most of the implementations only + check for interrupts that can be taken. */ + if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && + cpu_mips_hw_interrupts_pending(env)) { + has_work =3D true; + } + + /* MIPS-MT has the ability to halt the CPU. */ + if (env->CP0_Config3 & (1 << CP0C3_MT)) { + /* The QEMU model will issue an _WAKE request whenever the CPUs + should be woken up. */ + if (cs->interrupt_request & CPU_INTERRUPT_WAKE) { + has_work =3D true; + } + + if (!mips_vpe_active(env)) { + has_work =3D false; + } + } + return has_work; +} + /* CPUClass::reset() */ static void mips_cpu_reset(CPUState *s) { @@ -97,6 +126,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *= data) mcc->parent_reset =3D cc->reset; cc->reset =3D mips_cpu_reset; =20 + cc->has_work =3D mips_cpu_has_work; cc->do_interrupt =3D mips_cpu_do_interrupt; cc->dump_state =3D mips_cpu_dump_state; cc->set_pc =3D mips_cpu_set_pc; diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 60c8061..6981e7a 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -715,34 +715,6 @@ static inline int mips_vpe_active(CPUMIPSState *env) return active; } =20 -static inline bool cpu_has_work(CPUState *cpu) -{ - CPUMIPSState *env =3D &MIPS_CPU(cpu)->env; - bool has_work =3D false; - - /* It is implementation dependent if non-enabled interrupts - wake-up the CPU, however most of the implementations only - check for interrupts that can be taken. */ - if ((cpu->interrupt_request & CPU_INTERRUPT_HARD) && - cpu_mips_hw_interrupts_pending(env)) { - has_work =3D true; - } - - /* MIPS-MT has the ability to halt the CPU. */ - if (env->CP0_Config3 & (1 << CP0C3_MT)) { - /* The QEMU model will issue an _WAKE request whenever the CPUs - should be woken up. */ - if (cpu->interrupt_request & CPU_INTERRUPT_WAKE) { - has_work =3D true; - } - - if (!mips_vpe_active(env)) { - has_work =3D false; - } - } - return has_work; -} - #include "exec/exec-all.h" =20 static inline void compute_hflags(CPUMIPSState *env) diff --git a/target-moxie/cpu.c b/target-moxie/cpu.c index 484ecc2..88b0d35 100644 --- a/target-moxie/cpu.c +++ b/target-moxie/cpu.c @@ -29,6 +29,11 @@ static void moxie_cpu_set_pc(CPUState *cs, vaddr value= ) cpu->env.pc =3D value; } =20 +static bool moxie_cpu_has_work(CPUState *cs) +{ + return cs->interrupt_request & CPU_INTERRUPT_HARD; +} + static void moxie_cpu_reset(CPUState *s) { MoxieCPU *cpu =3D MOXIE_CPU(s); @@ -99,6 +104,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void= *data) =20 cc->class_by_name =3D moxie_cpu_class_by_name; =20 + cc->has_work =3D moxie_cpu_has_work; cc->do_interrupt =3D moxie_cpu_do_interrupt; cc->dump_state =3D moxie_cpu_dump_state; cc->set_pc =3D moxie_cpu_set_pc; diff --git a/target-moxie/cpu.h b/target-moxie/cpu.h index 5ce14b5..778cfc0 100644 --- a/target-moxie/cpu.h +++ b/target-moxie/cpu.h @@ -152,11 +152,6 @@ static inline void cpu_get_tb_cpu_state(CPUMoxieStat= e *env, target_ulong *pc, *flags =3D 0; } =20 -static inline int cpu_has_work(CPUState *cpu) -{ - return cpu->interrupt_request & CPU_INTERRUPT_HARD; -} - int cpu_moxie_handle_mmu_fault(CPUMoxieState *env, target_ulong address, int rw, int mmu_idx); =20 diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c index 8137943..83fed5e 100644 --- a/target-openrisc/cpu.c +++ b/target-openrisc/cpu.c @@ -27,6 +27,12 @@ static void openrisc_cpu_set_pc(CPUState *cs, vaddr va= lue) cpu->env.pc =3D value; } =20 +static bool openrisc_cpu_has_work(CPUState *cs) +{ + return cs->interrupt_request & (CPU_INTERRUPT_HARD | + CPU_INTERRUPT_TIMER); +} + /* CPUClass::reset() */ static void openrisc_cpu_reset(CPUState *s) { @@ -153,6 +159,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, = void *data) cc->reset =3D openrisc_cpu_reset; =20 cc->class_by_name =3D openrisc_cpu_class_by_name; + cc->has_work =3D openrisc_cpu_has_work; cc->do_interrupt =3D openrisc_cpu_do_interrupt; cc->dump_state =3D openrisc_cpu_dump_state; cc->set_pc =3D openrisc_cpu_set_pc; diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h index 51d6afd..ae9d17f 100644 --- a/target-openrisc/cpu.h +++ b/target-openrisc/cpu.h @@ -419,11 +419,6 @@ static inline int cpu_mmu_index(CPUOpenRISCState *en= v) } =20 #define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0 -static inline bool cpu_has_work(CPUState *cpu) -{ - return cpu->interrupt_request & (CPU_INTERRUPT_HARD | - CPU_INTERRUPT_TIMER); -} =20 #include "exec/exec-all.h" =20 diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index afab267..501dd03 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -2171,14 +2171,6 @@ static inline bool msr_is_64bit(CPUPPCState *env, = target_ulong msr) =20 extern void (*cpu_ppc_hypercall)(PowerPCCPU *); =20 -static inline bool cpu_has_work(CPUState *cpu) -{ - PowerPCCPU *ppc_cpu =3D POWERPC_CPU(cpu); - CPUPPCState *env =3D &ppc_cpu->env; - - return msr_ee && (cpu->interrupt_request & CPU_INTERRUPT_HARD); -} - #include "exec/exec-all.h" =20 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env); diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 3eafbb0..548ce09 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -8384,6 +8384,14 @@ static void ppc_cpu_set_pc(CPUState *cs, vaddr val= ue) cpu->env.nip =3D value; } =20 +static bool ppc_cpu_has_work(CPUState *cs) +{ + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + CPUPPCState *env =3D &cpu->env; + + return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); +} + /* CPUClass::reset() */ static void ppc_cpu_reset(CPUState *s) { @@ -8511,6 +8519,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->reset =3D ppc_cpu_reset; =20 cc->class_by_name =3D ppc_cpu_class_by_name; + cc->has_work =3D ppc_cpu_has_work; cc->do_interrupt =3D ppc_cpu_do_interrupt; cc->dump_state =3D ppc_cpu_dump_state; cc->dump_statistics =3D ppc_cpu_dump_statistics; diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c index 1a8c1cc..5dac322 100644 --- a/target-s390x/cpu.c +++ b/target-s390x/cpu.c @@ -65,6 +65,15 @@ static void s390_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.psw.addr =3D value; } =20 +static bool s390_cpu_has_work(CPUState *cs) +{ + S390CPU *cpu =3D S390_CPU(cs); + CPUS390XState *env =3D &cpu->env; + + return (cs->interrupt_request & CPU_INTERRUPT_HARD) && + (env->psw.mask & PSW_MASK_EXT); +} + #if !defined(CONFIG_USER_ONLY) /* S390CPUClass::load_normal() */ static void s390_cpu_load_normal(CPUState *s) @@ -232,6 +241,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void= *data) scc->cpu_reset =3D s390_cpu_reset; scc->initial_cpu_reset =3D s390_cpu_initial_reset; cc->reset =3D s390_cpu_full_reset; + cc->has_work =3D s390_cpu_has_work; cc->do_interrupt =3D s390_cpu_do_interrupt; cc->dump_state =3D s390_cpu_dump_state; cc->set_pc =3D s390_cpu_set_pc; diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h index effe84b..8b4a5c0 100644 --- a/target-s390x/cpu.h +++ b/target-s390x/cpu.h @@ -1041,15 +1041,6 @@ static inline void cpu_inject_crw_mchk(S390CPU *cp= u) cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); } =20 -static inline bool cpu_has_work(CPUState *cpu) -{ - S390CPU *s390_cpu =3D S390_CPU(cpu); - CPUS390XState *env =3D &s390_cpu->env; - - return (cpu->interrupt_request & CPU_INTERRUPT_HARD) && - (env->psw.mask & PSW_MASK_EXT); -} - /* fpu_helper.c */ uint32_t set_cc_nz_f32(float32 v); uint32_t set_cc_nz_f64(float64 v); diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c index c23294d..61b82f5 100644 --- a/target-sh4/cpu.c +++ b/target-sh4/cpu.c @@ -39,6 +39,11 @@ static void superh_cpu_synchronize_from_tb(CPUState *c= s, TranslationBlock *tb) cpu->env.flags =3D tb->flags; } =20 +static bool superh_cpu_has_work(CPUState *cs) +{ + return cs->interrupt_request & CPU_INTERRUPT_HARD; +} + /* CPUClass::reset() */ static void superh_cpu_reset(CPUState *s) { @@ -280,6 +285,7 @@ static void superh_cpu_class_init(ObjectClass *oc, vo= id *data) cc->reset =3D superh_cpu_reset; =20 cc->class_by_name =3D superh_cpu_class_by_name; + cc->has_work =3D superh_cpu_has_work; cc->do_interrupt =3D superh_cpu_do_interrupt; cc->dump_state =3D superh_cpu_dump_state; cc->set_pc =3D superh_cpu_set_pc; diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h index c181dda..808f90f 100644 --- a/target-sh4/cpu.h +++ b/target-sh4/cpu.h @@ -352,11 +352,6 @@ static inline void cpu_get_tb_cpu_state(CPUSH4State = *env, target_ulong *pc, | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 4= */ } =20 -static inline bool cpu_has_work(CPUState *cpu) -{ - return cpu->interrupt_request & CPU_INTERRUPT_HARD; -} - #include "exec/exec-all.h" =20 #endif /* _CPU_SH4_H */ diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c index 5806e59..6cf7e37 100644 --- a/target-sparc/cpu.c +++ b/target-sparc/cpu.c @@ -739,6 +739,15 @@ static void sparc_cpu_synchronize_from_tb(CPUState *= cs, TranslationBlock *tb) cpu->env.npc =3D tb->cs_base; } =20 +static bool sparc_cpu_has_work(CPUState *cs) +{ + SPARCCPU *cpu =3D SPARC_CPU(cs); + CPUSPARCState *env =3D &cpu->env; + + return (cs->interrupt_request & CPU_INTERRUPT_HARD) && + cpu_interrupts_enabled(env); +} + static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) { SPARCCPUClass *scc =3D SPARC_CPU_GET_CLASS(dev); @@ -782,6 +791,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, voi= d *data) scc->parent_reset =3D cc->reset; cc->reset =3D sparc_cpu_reset; =20 + cc->has_work =3D sparc_cpu_has_work; cc->do_interrupt =3D sparc_cpu_do_interrupt; cc->dump_state =3D sparc_cpu_dump_state; #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index ed6d2d1..e14b5a1 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -749,15 +749,6 @@ static inline bool tb_am_enabled(int tb_flags) #endif } =20 -static inline bool cpu_has_work(CPUState *cpu) -{ - SPARCCPU *sparc_cpu =3D SPARC_CPU(cpu); - CPUSPARCState *env1 =3D &sparc_cpu->env; - - return (cpu->interrupt_request & CPU_INTERRUPT_HARD) && - cpu_interrupts_enabled(env1); -} - #include "exec/exec-all.h" =20 #endif diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c index 3f78208..1cfe50a 100644 --- a/target-unicore32/cpu.c +++ b/target-unicore32/cpu.c @@ -23,6 +23,12 @@ static void uc32_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.regs[31] =3D value; } =20 +static bool uc32_cpu_has_work(CPUState *cs) +{ + return cs->interrupt_request & + (CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB); +} + static inline void set_feature(CPUUniCore32State *env, int feature) { env->features |=3D feature; @@ -138,6 +144,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void= *data) dc->realize =3D uc32_cpu_realizefn; =20 cc->class_by_name =3D uc32_cpu_class_by_name; + cc->has_work =3D uc32_cpu_has_work; cc->do_interrupt =3D uc32_cpu_do_interrupt; cc->dump_state =3D uc32_cpu_dump_state; cc->set_pc =3D uc32_cpu_set_pc; diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h index 967511e..1db7419 100644 --- a/target-unicore32/cpu.h +++ b/target-unicore32/cpu.h @@ -160,10 +160,4 @@ static inline void cpu_get_tb_cpu_state(CPUUniCore32= State *env, target_ulong *pc void uc32_translate_init(void); void switch_mode(CPUUniCore32State *, int); =20 -static inline bool cpu_has_work(CPUState *cpu) -{ - return cpu->interrupt_request & - (CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB); -} - #endif /* QEMU_UNICORE32_CPU_H */ diff --git a/target-xtensa/cpu.c b/target-xtensa/cpu.c index 749e205..6251f1c 100644 --- a/target-xtensa/cpu.c +++ b/target-xtensa/cpu.c @@ -40,6 +40,13 @@ static void xtensa_cpu_set_pc(CPUState *cs, vaddr valu= e) cpu->env.pc =3D value; } =20 +static bool xtensa_cpu_has_work(CPUState *cs) +{ + XtensaCPU *cpu =3D XTENSA_CPU(cs); + + return cpu->env.pending_irq_level; +} + /* CPUClass::reset() */ static void xtensa_cpu_reset(CPUState *s) { @@ -134,6 +141,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, vo= id *data) cc->reset =3D xtensa_cpu_reset; =20 cc->class_by_name =3D xtensa_cpu_class_by_name; + cc->has_work =3D xtensa_cpu_has_work; cc->do_interrupt =3D xtensa_cpu_do_interrupt; cc->dump_state =3D xtensa_cpu_dump_state; cc->set_pc =3D xtensa_cpu_set_pc; diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h index 3c7fa80..4bae693 100644 --- a/target-xtensa/cpu.h +++ b/target-xtensa/cpu.h @@ -525,11 +525,4 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaSta= te *env, target_ulong *pc, #include "exec/cpu-all.h" #include "exec/exec-all.h" =20 -static inline int cpu_has_work(CPUState *cpu) -{ - CPUXtensaState *env =3D &XTENSA_CPU(cpu)->env; - - return env->pending_irq_level; -} - #endif --=20 1.8.4.5