From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50748) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WO72f-0005cU-Mv for qemu-devel@nongnu.org; Thu, 13 Mar 2014 10:55:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WO72Z-0005zp-Kc for qemu-devel@nongnu.org; Thu, 13 Mar 2014 10:55:29 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Thu, 13 Mar 2014 15:54:28 +0100 Message-Id: <1394722501-32326-26-git-send-email-afaerber@suse.de> In-Reply-To: <1394722501-32326-1-git-send-email-afaerber@suse.de> References: <1394722501-32326-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PULL for-2.0-rc0 25/58] cpu: Factor out cpu_generic_init() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Jia Liu , Anthony Green , Alexander Graf , Michael Walle , "open list:PowerPC" , "Edgar E. Iglesias" , Guan Xuetao , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Aurelien Jarno All targets using it gain the ability to set -cpu name,key=3Dvalue,... options via the default TYPE_CPU CPUClass::parse_features() implementatio= n. Signed-off-by: Andreas F=C3=A4rber --- include/qom/cpu.h | 11 +++++++++++ qom/cpu.c | 41 +++++++++++++++++++++++++++++++++++++++= ++ target-arm/helper.c | 14 +------------- target-cris/cpu.c | 13 +------------ target-lm32/helper.c | 13 +------------ target-moxie/cpu.c | 13 +------------ target-openrisc/cpu.c | 13 +------------ target-ppc/translate_init.c | 21 +-------------------- target-sh4/cpu.c | 13 +------------ target-unicore32/helper.c | 13 +++---------- 10 files changed, 62 insertions(+), 103 deletions(-) diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 3703b68..f5b0d7a 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -352,6 +352,17 @@ void cpu_reset(CPUState *cpu); ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_mod= el); =20 /** + * cpu_generic_init: + * @typename: The CPU base type. + * @cpu_model: The model string including optional parameters. + * + * Instantiates a CPU, processes optional parameters and realizes the CP= U. + * + * Returns: A #CPUState or %NULL if an error occurred. + */ +CPUState *cpu_generic_init(const char *typename, const char *cpu_model); + +/** * cpu_has_work: * @cpu: The vCPU to check. * diff --git a/qom/cpu.c b/qom/cpu.c index 4aa0bf8..611ddf1 100644 --- a/qom/cpu.c +++ b/qom/cpu.c @@ -23,6 +23,7 @@ #include "sysemu/kvm.h" #include "qemu/notify.h" #include "qemu/log.h" +#include "qemu/error-report.h" #include "sysemu/sysemu.h" =20 bool cpu_exists(int64_t id) @@ -39,6 +40,46 @@ bool cpu_exists(int64_t id) return false; } =20 +CPUState *cpu_generic_init(const char *typename, const char *cpu_model) +{ + char *str, *name, *featurestr; + CPUState *cpu; + ObjectClass *oc; + CPUClass *cc; + Error *err =3D NULL; + + str =3D g_strdup(cpu_model); + name =3D strtok(str, ","); + + oc =3D cpu_class_by_name(typename, name); + if (oc =3D=3D NULL) { + g_free(str); + return NULL; + } + + cpu =3D CPU(object_new(object_class_get_name(oc))); + cc =3D CPU_GET_CLASS(cpu); + + featurestr =3D strtok(NULL, ","); + cc->parse_features(cpu, featurestr, &err); + g_free(str); + if (err !=3D NULL) { + goto out; + } + + object_property_set_bool(OBJECT(cpu), true, "realized", &err); + +out: + if (err !=3D NULL) { + error_report("%s", error_get_pretty(err)); + error_free(err); + object_unref(OBJECT(cpu)); + return NULL; + } + + return cpu; +} + bool cpu_paging_enabled(const CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); diff --git a/target-arm/helper.c b/target-arm/helper.c index a40f60f..f64be6f 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2186,19 +2186,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) =20 ARMCPU *cpu_arm_init(const char *cpu_model) { - ARMCPU *cpu; - ObjectClass *oc; - - oc =3D cpu_class_by_name(TYPE_ARM_CPU, cpu_model); - if (!oc) { - return NULL; - } - cpu =3D ARM_CPU(object_new(object_class_get_name(oc))); - - /* TODO this should be set centrally, once possible */ - object_property_set_bool(OBJECT(cpu), true, "realized", NULL); - - return cpu; + return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model)); } =20 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) diff --git a/target-cris/cpu.c b/target-cris/cpu.c index 07da845..12c90ee 100644 --- a/target-cris/cpu.c +++ b/target-cris/cpu.c @@ -89,18 +89,7 @@ static ObjectClass *cris_cpu_class_by_name(const char = *cpu_model) =20 CRISCPU *cpu_cris_init(const char *cpu_model) { - CRISCPU *cpu; - ObjectClass *oc; - - oc =3D cris_cpu_class_by_name(cpu_model); - if (oc =3D=3D NULL) { - return NULL; - } - cpu =3D CRIS_CPU(object_new(object_class_get_name(oc))); - - object_property_set_bool(OBJECT(cpu), true, "realized", NULL); - - return cpu; + return CRIS_CPU(cpu_generic_init(TYPE_CRIS_CPU, cpu_model)); } =20 /* Sort alphabetically by VR. */ diff --git a/target-lm32/helper.c b/target-lm32/helper.c index eecb9f6..e813e7d 100644 --- a/target-lm32/helper.c +++ b/target-lm32/helper.c @@ -182,18 +182,7 @@ void lm32_cpu_do_interrupt(CPUState *cs) =20 LM32CPU *cpu_lm32_init(const char *cpu_model) { - LM32CPU *cpu; - ObjectClass *oc; - - oc =3D cpu_class_by_name(TYPE_LM32_CPU, cpu_model); - if (oc =3D=3D NULL) { - return NULL; - } - cpu =3D LM32_CPU(object_new(object_class_get_name(oc))); - - object_property_set_bool(OBJECT(cpu), true, "realized", NULL); - - return cpu; + return LM32_CPU(cpu_generic_init(TYPE_LM32_CPU, cpu_model)); } =20 /* Some soc ignores the MSB on the address bus. Thus creating a shadow m= emory diff --git a/target-moxie/cpu.c b/target-moxie/cpu.c index 88b0d35..32c6104 100644 --- a/target-moxie/cpu.c +++ b/target-moxie/cpu.c @@ -136,18 +136,7 @@ static const MoxieCPUInfo moxie_cpus[] =3D { =20 MoxieCPU *cpu_moxie_init(const char *cpu_model) { - MoxieCPU *cpu; - ObjectClass *oc; - - oc =3D moxie_cpu_class_by_name(cpu_model); - if (oc =3D=3D NULL) { - return NULL; - } - cpu =3D MOXIE_CPU(object_new(object_class_get_name(oc))); - - object_property_set_bool(OBJECT(cpu), true, "realized", NULL); - - return cpu; + return MOXIE_CPU(cpu_generic_init(TYPE_MOXIE_CPU, cpu_model)); } =20 static void cpu_register(const MoxieCPUInfo *info) diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c index 83fed5e..0b2ffb2 100644 --- a/target-openrisc/cpu.c +++ b/target-openrisc/cpu.c @@ -208,18 +208,7 @@ static void openrisc_cpu_register_types(void) =20 OpenRISCCPU *cpu_openrisc_init(const char *cpu_model) { - OpenRISCCPU *cpu; - ObjectClass *oc; - - oc =3D openrisc_cpu_class_by_name(cpu_model); - if (oc =3D=3D NULL) { - return NULL; - } - cpu =3D OPENRISC_CPU(object_new(object_class_get_name(oc))); - - object_property_set_bool(OBJECT(cpu), true, "realized", NULL); - - return cpu; + return OPENRISC_CPU(cpu_generic_init(TYPE_OPENRISC_CPU, cpu_model)); } =20 /* Sort alphabetically by type name, except for "any". */ diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 548ce09..0418f06 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -8220,26 +8220,7 @@ static ObjectClass *ppc_cpu_class_by_name(const ch= ar *name) =20 PowerPCCPU *cpu_ppc_init(const char *cpu_model) { - PowerPCCPU *cpu; - ObjectClass *oc; - Error *err =3D NULL; - - oc =3D ppc_cpu_class_by_name(cpu_model); - if (oc =3D=3D NULL) { - return NULL; - } - - cpu =3D POWERPC_CPU(object_new(object_class_get_name(oc))); - - object_property_set_bool(OBJECT(cpu), true, "realized", &err); - if (err !=3D NULL) { - error_report("%s", error_get_pretty(err)); - error_free(err); - object_unref(OBJECT(cpu)); - return NULL; - } - - return cpu; + return POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, cpu_model)); } =20 /* Sort by PVR, ordering special case "host" last. */ diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c index 61b82f5..8e7bcd2 100644 --- a/target-sh4/cpu.c +++ b/target-sh4/cpu.c @@ -148,18 +148,7 @@ static ObjectClass *superh_cpu_class_by_name(const c= har *cpu_model) =20 SuperHCPU *cpu_sh4_init(const char *cpu_model) { - SuperHCPU *cpu; - ObjectClass *oc; - - oc =3D superh_cpu_class_by_name(cpu_model); - if (oc =3D=3D NULL) { - return NULL; - } - cpu =3D SUPERH_CPU(object_new(object_class_get_name(oc))); - - object_property_set_bool(OBJECT(cpu), true, "realized", NULL); - - return cpu; + return SUPERH_CPU(cpu_generic_init(TYPE_SUPERH_CPU, cpu_model)); } =20 static void sh7750r_cpu_initfn(Object *obj) diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c index 9bf4fea..a1f86b0 100644 --- a/target-unicore32/helper.c +++ b/target-unicore32/helper.c @@ -28,19 +28,12 @@ CPUUniCore32State *uc32_cpu_init(const char *cpu_model) { UniCore32CPU *cpu; - CPUUniCore32State *env; - ObjectClass *oc; =20 - oc =3D cpu_class_by_name(TYPE_UNICORE32_CPU, cpu_model); - if (oc =3D=3D NULL) { + cpu =3D UNICORE32_CPU(cpu_generic_init(TYPE_UNICORE32_CPU, cpu_model= )); + if (cpu =3D=3D NULL) { return NULL; } - cpu =3D UNICORE32_CPU(object_new(object_class_get_name(oc))); - env =3D &cpu->env; - - object_property_set_bool(OBJECT(cpu), true, "realized", NULL); - - return env; + return &cpu->env; } =20 uint32_t HELPER(clo)(uint32_t x) --=20 1.8.4.5