From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51075) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WO72y-0005wl-S4 for qemu-devel@nongnu.org; Thu, 13 Mar 2014 10:55:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WO72r-00069W-Hn for qemu-devel@nongnu.org; Thu, 13 Mar 2014 10:55:48 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Thu, 13 Mar 2014 15:54:43 +0100 Message-Id: <1394722501-32326-41-git-send-email-afaerber@suse.de> In-Reply-To: <1394722501-32326-1-git-send-email-afaerber@suse.de> References: <1394722501-32326-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PULL for-2.0-rc0 40/58] translate-all: Change cpu_restore_state() argument to CPUState List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Jia Liu , "Michael S. Tsirkin" , Anthony Green , Alexander Graf , Blue Swirl , Max Filippov , Michael Walle , "open list:PowerPC" , Anthony Liguori , "Edgar E. Iglesias" , Guan Xuetao , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Aurelien Jarno , Richard Henderson This lets us drop some local variables in tlb_fill() functions. Signed-off-by: Andreas F=C3=A4rber --- hw/i386/kvmvapic.c | 2 +- include/exec/exec-all.h | 2 +- target-alpha/helper.c | 2 +- target-alpha/mem_helper.c | 7 ++----- target-arm/op_helper.c | 2 +- target-cris/op_helper.c | 2 +- target-i386/helper.c | 2 +- target-i386/mem_helper.c | 2 +- target-lm32/op_helper.c | 5 +---- target-m68k/op_helper.c | 5 +---- target-microblaze/op_helper.c | 5 +---- target-mips/op_helper.c | 2 +- target-moxie/helper.c | 6 ++---- target-openrisc/mmu_helper.c | 5 +---- target-ppc/mmu_helper.c | 2 +- target-s390x/mem_helper.c | 5 +---- target-s390x/misc_helper.c | 2 +- target-sh4/op_helper.c | 7 ++----- target-sparc/helper.c | 20 ++++++++++++++------ target-sparc/ldst_helper.c | 8 +++----- target-unicore32/op_helper.c | 5 +---- target-xtensa/op_helper.c | 6 ++++-- translate-all.c | 3 ++- user-exec.c | 2 +- 24 files changed, 46 insertions(+), 63 deletions(-) diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c index 6cf5d41..39d516a 100644 --- a/hw/i386/kvmvapic.c +++ b/hw/i386/kvmvapic.c @@ -406,7 +406,7 @@ static void patch_instruction(VAPICROMState *s, X86CP= U *cpu, target_ulong ip) } =20 if (!kvm_enabled()) { - cpu_restore_state(env, cs->mem_io_pc); + cpu_restore_state(cs, cs->mem_io_pc); cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, ¤t_flags); } diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 80277ea..cf5cd71 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -80,7 +80,7 @@ void restore_state_to_opc(CPUArchState *env, struct Tra= nslationBlock *tb, void cpu_gen_init(void); int cpu_gen_code(CPUArchState *env, struct TranslationBlock *tb, int *gen_code_size_ptr); -bool cpu_restore_state(CPUArchState *env, uintptr_t searched_pc); +bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc); void page_size_init(void); =20 void QEMU_NORETURN cpu_resume_from_signal(CPUArchState *env1, void *puc)= ; diff --git a/target-alpha/helper.c b/target-alpha/helper.c index 45f73e0..305dd67 100644 --- a/target-alpha/helper.c +++ b/target-alpha/helper.c @@ -526,7 +526,7 @@ void QEMU_NORETURN dynamic_excp(CPUAlphaState *env, u= intptr_t retaddr, cs->exception_index =3D excp; env->error_code =3D error; if (retaddr) { - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } cpu_loop_exit(cs); } diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c index 1957c56..5964bdc 100644 --- a/target-alpha/mem_helper.c +++ b/target-alpha/mem_helper.c @@ -105,7 +105,7 @@ static void do_unaligned_access(CPUAlphaState *env, t= arget_ulong addr, uint32_t insn; =20 if (retaddr) { - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } =20 pc =3D env->pc; @@ -159,11 +159,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, int i= s_write, =20 ret =3D alpha_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret !=3D 0)) { - AlphaCPU *cpu =3D ALPHA_CPU(cs); - CPUAlphaState *env =3D &cpu->env; - if (retaddr) { - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } /* Exception index and error code are already set */ cpu_loop_exit(cs); diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index f8e535e..21ff58e 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -87,7 +87,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_w= rite, int mmu_idx, =20 if (retaddr) { /* now we have a real cpu fault */ - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } raise_exception(env, cs->exception_index); } diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c index d80b6c9..d28bd61 100644 --- a/target-cris/op_helper.c +++ b/target-cris/op_helper.c @@ -67,7 +67,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_w= rite, int mmu_idx, if (unlikely(ret)) { if (retaddr) { /* now we have a real cpu fault */ - if (cpu_restore_state(env, retaddr)) { + if (cpu_restore_state(cs, retaddr)) { /* Evaluate flags after retranslation. */ helper_top_evaluate_flags(env); } diff --git a/target-i386/helper.c b/target-i386/helper.c index 59736d7..cb29aa4 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -1263,7 +1263,7 @@ void cpu_report_tpr_access(CPUX86State *env, TPRAcc= ess access) =20 cpu_interrupt(cs, CPU_INTERRUPT_TPR); } else { - cpu_restore_state(env, cs->mem_io_pc); + cpu_restore_state(cs, cs->mem_io_pc); =20 apic_handle_tpr_access_report(cpu->apic_state, env->eip, access)= ; } diff --git a/target-i386/mem_helper.c b/target-i386/mem_helper.c index 2f0691b..b3b811b 100644 --- a/target-i386/mem_helper.c +++ b/target-i386/mem_helper.c @@ -145,7 +145,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is= _write, int mmu_idx, =20 if (retaddr) { /* now we have a real cpu fault */ - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } raise_exception_err(env, cs->exception_index, env->error_code); } diff --git a/target-lm32/op_helper.c b/target-lm32/op_helper.c index f0859aa..2f36b7b 100644 --- a/target-lm32/op_helper.c +++ b/target-lm32/op_helper.c @@ -160,12 +160,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int i= s_write, int mmu_idx, =20 ret =3D lm32_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret)) { - LM32CPU *cpu =3D LM32_CPU(cs); - CPULM32State *env =3D &cpu->env; - if (retaddr) { /* now we have a real cpu fault */ - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } cpu_loop_exit(cs); } diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c index d6268cd..06302b1 100644 --- a/target-m68k/op_helper.c +++ b/target-m68k/op_helper.c @@ -60,12 +60,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_= write, int mmu_idx, =20 ret =3D m68k_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret)) { - M68kCPU *cpu =3D M68K_CPU(cs); - CPUM68KState *env =3D &cpu->env; - if (retaddr) { /* now we have a real cpu fault */ - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } cpu_loop_exit(cs); } diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.= c index f476132..f8fb7f9 100644 --- a/target-microblaze/op_helper.c +++ b/target-microblaze/op_helper.c @@ -49,12 +49,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_= write, int mmu_idx, =20 ret =3D mb_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret)) { - MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); - CPUMBState *env =3D &cpu->env; - if (retaddr) { /* now we have a real cpu fault */ - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } cpu_loop_exit(cs); } diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index c653501..de5a223 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -48,7 +48,7 @@ static inline void QEMU_NORETURN do_raise_exception_err= (CPUMIPSState *env, =20 if (pc) { /* now we have a real cpu fault */ - cpu_restore_state(env, pc); + cpu_restore_state(cs, pc); } =20 cpu_loop_exit(cs); diff --git a/target-moxie/helper.c b/target-moxie/helper.c index 3994c09..04b36b7 100644 --- a/target-moxie/helper.c +++ b/target-moxie/helper.c @@ -49,14 +49,12 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx= , uintptr_t retaddr) { - MoxieCPU *cpu =3D MOXIE_CPU(cs); - CPUMoxieState *env =3D &cpu->env; int ret; =20 ret =3D moxie_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret)) { if (retaddr) { - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } } cpu_loop_exit(cs); @@ -70,7 +68,7 @@ void helper_raise_exception(CPUMoxieState *env, int ex) /* Stash the exception type. */ env->sregs[2] =3D ex; /* Stash the address where the exception occurred. */ - cpu_restore_state(env, GETPC()); + cpu_restore_state(cs, GETPC()); env->sregs[5] =3D env->pc; /* Jump the the exception handline routine. */ env->pc =3D env->sregs[1]; diff --git a/target-openrisc/mmu_helper.c b/target-openrisc/mmu_helper.c index 5f7f6f5..fb457c7 100644 --- a/target-openrisc/mmu_helper.c +++ b/target-openrisc/mmu_helper.c @@ -44,12 +44,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_= write, ret =3D openrisc_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); =20 if (ret) { - OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); - CPUOpenRISCState *env =3D &cpu->env; - if (retaddr) { /* now we have a real cpu fault. */ - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } /* Raise Exception. */ cpu_loop_exit(cs); diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index c042184..2a94f3d 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -2909,7 +2909,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int = is_write, int mmu_idx, if (unlikely(ret !=3D 0)) { if (likely(retaddr)) { /* now we have a real cpu fault */ - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } helper_raise_exception_err(env, cs->exception_index, env->error_= code); } diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c index e89fcac..e1c2ac0 100644 --- a/target-s390x/mem_helper.c +++ b/target-s390x/mem_helper.c @@ -51,12 +51,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_= write, int mmu_idx, =20 ret =3D s390_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret !=3D 0)) { - S390CPU *cpu =3D S390_CPU(cs); - CPUS390XState *env =3D &cpu->env; - if (likely(retaddr)) { /* now we have a real cpu fault */ - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } cpu_loop_exit(cs); } diff --git a/target-s390x/misc_helper.c b/target-s390x/misc_helper.c index 2beec61..942b5f7 100644 --- a/target-s390x/misc_helper.c +++ b/target-s390x/misc_helper.c @@ -54,7 +54,7 @@ void QEMU_NORETURN runtime_exception(CPUS390XState *env= , int excp, env->int_pgm_code =3D excp; =20 /* Use the (ultimate) callers address to find the insn that trapped.= */ - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); =20 /* Advance past the insn. */ t =3D cpu_ldub_code(env, env->psw.addr); diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c index 271401f..b3ce7ba 100644 --- a/target-sh4/op_helper.c +++ b/target-sh4/op_helper.c @@ -46,11 +46,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_= write, int mmu_idx, ret =3D superh_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (ret) { /* now we have a real cpu fault */ - SuperHCPU *cpu =3D SUPERH_CPU(cs); - CPUSH4State *env =3D &cpu->env; - if (retaddr) { - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } cpu_loop_exit(cs); } @@ -75,7 +72,7 @@ static inline void QEMU_NORETURN raise_exception(CPUSH4= State *env, int index, =20 cs->exception_index =3D index; if (retaddr) { - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } cpu_loop_exit(cs); } diff --git a/target-sparc/helper.c b/target-sparc/helper.c index fb5f6ec..f3c7fbf 100644 --- a/target-sparc/helper.c +++ b/target-sparc/helper.c @@ -71,6 +71,7 @@ void helper_tick_set_limit(void *opaque, uint64_t limit= ) static target_ulong helper_udiv_common(CPUSPARCState *env, target_ulong = a, target_ulong b, int cc) { + SPARCCPU *cpu =3D sparc_env_get_cpu(env); int overflow =3D 0; uint64_t x0; uint32_t x1; @@ -79,7 +80,7 @@ static target_ulong helper_udiv_common(CPUSPARCState *e= nv, target_ulong a, x1 =3D (b & 0xffffffff); =20 if (x1 =3D=3D 0) { - cpu_restore_state(env, GETPC()); + cpu_restore_state(CPU(cpu), GETPC()); helper_raise_exception(env, TT_DIV_ZERO); } =20 @@ -110,6 +111,7 @@ target_ulong helper_udiv_cc(CPUSPARCState *env, targe= t_ulong a, target_ulong b) static target_ulong helper_sdiv_common(CPUSPARCState *env, target_ulong = a, target_ulong b, int cc) { + SPARCCPU *cpu =3D sparc_env_get_cpu(env); int overflow =3D 0; int64_t x0; int32_t x1; @@ -118,7 +120,7 @@ static target_ulong helper_sdiv_common(CPUSPARCState = *env, target_ulong a, x1 =3D (b & 0xffffffff); =20 if (x1 =3D=3D 0) { - cpu_restore_state(env, GETPC()); + cpu_restore_state(CPU(cpu), GETPC()); helper_raise_exception(env, TT_DIV_ZERO); } =20 @@ -151,7 +153,9 @@ int64_t helper_sdivx(CPUSPARCState *env, int64_t a, i= nt64_t b) { if (b =3D=3D 0) { /* Raise divide by zero trap. */ - cpu_restore_state(env, GETPC()); + SPARCCPU *cpu =3D sparc_env_get_cpu(env); + + cpu_restore_state(CPU(cpu), GETPC()); helper_raise_exception(env, TT_DIV_ZERO); } else if (b =3D=3D -1) { /* Avoid overflow trap with i386 divide insn. */ @@ -165,7 +169,9 @@ uint64_t helper_udivx(CPUSPARCState *env, uint64_t a,= uint64_t b) { if (b =3D=3D 0) { /* Raise divide by zero trap. */ - cpu_restore_state(env, GETPC()); + SPARCCPU *cpu =3D sparc_env_get_cpu(env); + + cpu_restore_state(CPU(cpu), GETPC()); helper_raise_exception(env, TT_DIV_ZERO); } return a / b; @@ -175,6 +181,7 @@ uint64_t helper_udivx(CPUSPARCState *env, uint64_t a,= uint64_t b) target_ulong helper_taddcctv(CPUSPARCState *env, target_ulong src1, target_ulong src2) { + SPARCCPU *cpu =3D sparc_env_get_cpu(env); target_ulong dst; =20 /* Tag overflow occurs if either input has bits 0 or 1 set. */ @@ -197,13 +204,14 @@ target_ulong helper_taddcctv(CPUSPARCState *env, ta= rget_ulong src1, return dst; =20 tag_overflow: - cpu_restore_state(env, GETPC()); + cpu_restore_state(CPU(cpu), GETPC()); helper_raise_exception(env, TT_TOVF); } =20 target_ulong helper_tsubcctv(CPUSPARCState *env, target_ulong src1, target_ulong src2) { + SPARCCPU *cpu =3D sparc_env_get_cpu(env); target_ulong dst; =20 /* Tag overflow occurs if either input has bits 0 or 1 set. */ @@ -226,7 +234,7 @@ target_ulong helper_tsubcctv(CPUSPARCState *env, targ= et_ulong src1, return dst; =20 tag_overflow: - cpu_restore_state(env, GETPC()); + cpu_restore_state(CPU(cpu), GETPC()); helper_raise_exception(env, TT_TOVF); } =20 diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c index 8302bb1..1f6df49 100644 --- a/target-sparc/ldst_helper.c +++ b/target-sparc/ldst_helper.c @@ -2424,12 +2424,13 @@ static void QEMU_NORETURN do_unaligned_access(CPU= SPARCState *env, target_ulong addr, int is_= write, int is_user, uintptr_t ret= addr) { + SPARCCPU *cpu =3D sparc_env_get_cpu(env); #ifdef DEBUG_UNALIGNED printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_= lx "\n", addr, env->pc); #endif if (retaddr) { - cpu_restore_state(env, retaddr); + cpu_restore_state(CPU(cpu), retaddr); } helper_raise_exception(env, TT_UNALIGNED); } @@ -2445,11 +2446,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, int= is_write, int mmu_idx, =20 ret =3D sparc_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (ret) { - SPARCCPU *cpu =3D SPARC_CPU(cs); - CPUSPARCState *env =3D &cpu->env; - if (retaddr) { - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } cpu_loop_exit(cs); } diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c index c2bf834..4c6950d 100644 --- a/target-unicore32/op_helper.c +++ b/target-unicore32/op_helper.c @@ -264,12 +264,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int i= s_write, =20 ret =3D uc32_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret)) { - UniCore32CPU *cpu =3D UNICORE32_CPU(cs); - CPUUniCore32State *env =3D &cpu->env; - if (retaddr) { /* now we have a real cpu fault */ - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); } cpu_loop_exit(cs); } diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c index 4265378..8233443 100644 --- a/target-xtensa/op_helper.c +++ b/target-xtensa/op_helper.c @@ -52,9 +52,11 @@ static void do_unaligned_access(CPUXtensaState *env, static void do_unaligned_access(CPUXtensaState *env, target_ulong addr, int is_write, int is_user, uintptr_t retaddr) { + XtensaCPU *cpu =3D xtensa_env_get_cpu(env); + if (xtensa_option_enabled(env->config, XTENSA_OPTION_UNALIGNED_EXCEP= TION) && !xtensa_option_enabled(env->config, XTENSA_OPTION_HW_ALIGNME= NT)) { - cpu_restore_state(env, retaddr); + cpu_restore_state(CPU(cpu), retaddr); HELPER(exception_cause_vaddr)(env, env->pc, LOAD_STORE_ALIGNMENT_CAUSE, addr); } @@ -80,7 +82,7 @@ void tlb_fill(CPUState *cs, paddr & TARGET_PAGE_MASK, access, mmu_idx, page_size); } else { - cpu_restore_state(env, retaddr); + cpu_restore_state(cs, retaddr); HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr); } } diff --git a/translate-all.c b/translate-all.c index c067011..70d8229 100644 --- a/translate-all.c +++ b/translate-all.c @@ -253,8 +253,9 @@ static int cpu_restore_state_from_tb(TranslationBlock= *tb, CPUArchState *env, return 0; } =20 -bool cpu_restore_state(CPUArchState *env, uintptr_t retaddr) +bool cpu_restore_state(CPUState *cpu, uintptr_t retaddr) { + CPUArchState *env =3D cpu->env_ptr; TranslationBlock *tb; =20 tb =3D tb_find_pc(retaddr); diff --git a/user-exec.c b/user-exec.c index e149c97..75c6d54 100644 --- a/user-exec.c +++ b/user-exec.c @@ -117,7 +117,7 @@ static inline int handle_cpu_signal(uintptr_t pc, uns= igned long address, return 1; /* the MMU fault was handled without causing real CPU = fault */ } /* now we have a real cpu fault */ - cpu_restore_state(env, pc); + cpu_restore_state(cpu, pc); =20 /* we restore the process signal mask as the sigreturn should do it (XXX: use sigsetjmp) */ --=20 1.8.4.5