From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44390) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WOWkr-0003HO-TP for qemu-devel@nongnu.org; Fri, 14 Mar 2014 14:22:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WOWkm-0004kP-HN for qemu-devel@nongnu.org; Fri, 14 Mar 2014 14:22:49 -0400 Received: from mail-oa0-x22e.google.com ([2607:f8b0:4003:c02::22e]:45462) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WOWkm-0004kI-C7 for qemu-devel@nongnu.org; Fri, 14 Mar 2014 14:22:44 -0400 Received: by mail-oa0-f46.google.com with SMTP id i7so3010747oag.33 for ; Fri, 14 Mar 2014 11:22:43 -0700 (PDT) From: Rob Herring Date: Fri, 14 Mar 2014 13:22:29 -0500 Message-Id: <1394821351-21477-3-git-send-email-robherring2@gmail.com> In-Reply-To: <1394821351-21477-1-git-send-email-robherring2@gmail.com> References: <1394821351-21477-1-git-send-email-robherring2@gmail.com> Subject: [Qemu-devel] [PATCH v2 2/4] pl011: fix UARTRSR accesses corrupting the UARTCR value List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, Peter Maydell Cc: Rob Herring From: Rob Herring Offset 4 is UARTRSR/UARTECR, not the UARTCR. The UARTCR would be corrupted if the UARTRSR is ever written. Fix by implementing a correct model of the UARTRSR/UARTECR register. Reads of this register simply reflect the error bits in data register. Only breaks can be triggered in QEMU. With the pl011_can_receive function, we effectively have flow control between the host and the model. Framing and parity errors simply don't make sense in the model and will never occur. Signed-off-by: Rob Herring --- hw/char/pl011.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index f0c3fa3..920ba3f 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -20,6 +20,7 @@ typedef struct PL011State { uint32_t readbuff; uint32_t flags; uint32_t lcr; + uint32_t rsr; uint32_t cr; uint32_t dmacr; uint32_t int_enabled; @@ -81,13 +82,14 @@ static uint64_t pl011_read(void *opaque, hwaddr offset, } if (s->read_count == s->read_trigger - 1) s->int_level &= ~ PL011_INT_RX; + s->rsr = c >> 8; pl011_update(s); if (s->chr) { qemu_chr_accept_input(s->chr); } return c; - case 1: /* UARTCR */ - return 0; + case 1: /* UARTRSR */ + return s->rsr; case 6: /* UARTFR */ return s->flags; case 8: /* UARTILPR */ @@ -146,8 +148,8 @@ static void pl011_write(void *opaque, hwaddr offset, s->int_level |= PL011_INT_TX; pl011_update(s); break; - case 1: /* UARTCR */ - s->cr = value; + case 1: /* UARTRSR/UARTECR */ + s->rsr = 0; break; case 6: /* UARTFR */ /* Writes to Flag register are ignored. */ -- 1.8.3.2