From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44396) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WOWks-0003HP-JQ for qemu-devel@nongnu.org; Fri, 14 Mar 2014 14:22:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WOWkn-0004ke-8s for qemu-devel@nongnu.org; Fri, 14 Mar 2014 14:22:50 -0400 Received: from mail-oa0-x232.google.com ([2607:f8b0:4003:c02::232]:36869) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WOWkn-0004kT-4M for qemu-devel@nongnu.org; Fri, 14 Mar 2014 14:22:45 -0400 Received: by mail-oa0-f50.google.com with SMTP id i7so3036154oag.9 for ; Fri, 14 Mar 2014 11:22:44 -0700 (PDT) From: Rob Herring Date: Fri, 14 Mar 2014 13:22:30 -0500 Message-Id: <1394821351-21477-4-git-send-email-robherring2@gmail.com> In-Reply-To: <1394821351-21477-1-git-send-email-robherring2@gmail.com> References: <1394821351-21477-1-git-send-email-robherring2@gmail.com> Subject: [Qemu-devel] [PATCH v2 3/4] pl011: fix incorrect logic to set the RXFF flag List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, Peter Maydell Cc: Rob Herring From: Rob Herring The receive fifo full bit should be set when 1 character is received and the fifo is disabled or when 16 characters are in the fifo. Signed-off-by: Rob Herring --- hw/char/pl011.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 920ba3f..5e664f4 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -220,7 +220,7 @@ static void pl011_put_fifo(void *opaque, uint32_t value) s->read_fifo[slot] = value; s->read_count++; s->flags &= ~PL011_FLAG_RXFE; - if (s->cr & 0x10 || s->read_count == 16) { + if (!(s->lcr & 0x10) || s->read_count == 16) { s->flags |= PL011_FLAG_RXFF; } if (s->read_count == s->read_trigger) { -- 1.8.3.2