From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44409) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WOWkv-0003Iu-OH for qemu-devel@nongnu.org; Fri, 14 Mar 2014 14:22:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WOWko-0004ks-9r for qemu-devel@nongnu.org; Fri, 14 Mar 2014 14:22:53 -0400 Received: from mail-ob0-x232.google.com ([2607:f8b0:4003:c01::232]:51252) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WOWko-0004kk-5B for qemu-devel@nongnu.org; Fri, 14 Mar 2014 14:22:46 -0400 Received: by mail-ob0-f178.google.com with SMTP id wp18so2970139obc.9 for ; Fri, 14 Mar 2014 11:22:45 -0700 (PDT) From: Rob Herring Date: Fri, 14 Mar 2014 13:22:31 -0500 Message-Id: <1394821351-21477-5-git-send-email-robherring2@gmail.com> In-Reply-To: <1394821351-21477-1-git-send-email-robherring2@gmail.com> References: <1394821351-21477-1-git-send-email-robherring2@gmail.com> Subject: [Qemu-devel] [PATCH v2 4/4] pl011: re-evaluate rx interrupt when fifo trigger changes List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, Peter Maydell Cc: Rob Herring From: Rob Herring When setting the fifo trigger level, the rx interrupt needs to be asserted if the current fifo level matches. This is more for correctness as the level is currently never changed. Signed-off-by: Rob Herring --- hw/char/pl011.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 5e664f4..3903933 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -131,6 +131,10 @@ static void pl011_set_read_trigger(PL011State *s) else #endif s->read_trigger = 1; + + if (s->read_count == s->read_trigger) { + s->int_level |= PL011_INT_RX; + } } static void pl011_write(void *opaque, hwaddr offset, -- 1.8.3.2